Glenayre Electronics, Inc.

Robert F Marchetto

Todd A Stewart

Glenn S Fawcett

Paul K Ho

Paul Andrew Goud

Timothy Jay Linderer

Charles Brian Cox

David W Kroeger

Richard Johnathan Hinkle

Robert J Shade

A modulator that modulates and encodes data using data symbols, interspersed with pilot symbols, for transmission to another modem, and a demodulator that decodes data symbols of a signal received from another modem. In the demodulator, a received signal is sampled at four times the symbol rate. The sampled signal is converted to quadrature signals and low-pass filtered to produce a complex baseband signal. Data symbols in the complex baseband signal are sampled in synchronization with the start of each symbol based on the pilot symbols that are interspersed in the signal. By processing the pilot symbols, full modem synchronization is maintained down to a very low signal-to-noise ratio, through noise bursts, or even when the data symbols representing data are replaced by predefined sequences of data symbols that convey the dots and dashes of Morse code identifying the station transmitting the modulated signal. The continued presence of pilot symbols interspersed with the sequences of data symbols conveying Morse code prevents loss of synchronization between the transmitting station and the receiving station. The pilot symbols are also used to update equalizer tap coefficients in an equalizer of the demodulator, thereby minimizing errors in the output data caused by channel fading, noise, and other effects. In addition, the sequence of pilot symbols is used to delimit data frames, so that bit synchronization and frame synchronization in the data are not required.

Signal modulation employing a pseudo-random sequence of pilot symbols

High performance modem using pilot symbols for equalization and frame

In a simulcast communication system, a method and apparatus for compensating differences in propagation time, lack of synchronization in transmitters, and multipath fading to recover data transmitted to a receiving device. In a simulcast communication system(26) that comprises a plurality of transmitters (32), a receiver (36) includes a digital signal processor (DSP) (86) that processes a demodulated received signal to adaptively compensate for changes in the channel through which a multipath signal is propagated from the transmitters to the receiver. In one embodiment, the DSP comprises a decision feedback equalizer. An error signal is produced by the equalizer through a comparison of the estimated symbols with symbols most likely transmitted, for use in updating filter coefficients used by the equalizer in processing the received signal. Alternatively, in a linear adaptive equalizer, reference or pilot symbols transmitted with the data symbols are used to determine the error signal. Another embodiment implements a Viterbi algorithm to make decisions of the most likely data symbols in response to estimates of the channel impulse response. Further, a hybrid embodiment combines the Viterbi decoder with a bi-directional decision feedback equalizer that produces forward and reverse estimates of the sequence of data symbols. The Viterbi decoder selects between the forward and reverse sequences based upon channel impulse response estimates to dynamically compensate for varying channel conditions. Using any one of these embodiments, a linear modulated signal can be decoded to recover the data transmitted, even though the received signal has been degraded by propagation in a multipath fading channel. The same techniques are also disclosed as applicable to constant envelope modulated transmissions in a simulcast system.

High speed simulcast data system using adaptive compensation

A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay. As each sampled digital value is produced, the delayed value is output and converted by a digital-to-analog converter (DAC) 54 in the CODEC to an analog signal having the corresponding required delay. By thus providing the appropriate equalization time delay to the signal transmitted by each paging transmitter in a simulcast paging system 20, differences in the time required for the analog signal to propagate from a paging terminal to each paging transmitter are compensated, thereby substantially eliminating phase interference in overlap zones of the paging transmitters.

Digital signal processor delay equalization for use in a paging system

A digital exciter (30) for selectively modulating digital or analog input data. The digital exciter includes a digital signal modulator (32) and a digital quadrature modulator (DQM)(36) comprising two digital signal processors (DSPs). The signal modulator is controlled by a control (40). An operator can selectively determine whether the digital exciter is used for modulating either two level or four level NRZ digital data and whether the device is to provide linear modulation or frequency modulation (FM) of the input signal. An interpolator (38) interpolates a 662/3 kHz timer interrupt rate used in the signal modulator to a 400 kHz rate, thereby reducing the processing load on the DSP comprising the DQM by simplifying the sine and cosine values used in the quadrature modulation. An operator can select from among a plurality of operating parameters on a menu for controlling the signal modulator, either from a local or a remote video display terminal (VDT).

Digital signal processor exciter

A method and apparatus for compensating fading and interference in a radio signal. A plurality of pilot symbols are appended to a plurality of data symbols to form successive frames that are modulated at a transmitter. The transmitted modulated signal is subject to loss of data due to simple fading and multi-path and simulcast interference. The received signals are demodulated by a receiver and processed to provide a data signal comprising the data symbols and a pilot signal comprising the pilot symbols. The data signal is delayed for sufficient time to enable channel impulse response estimates to be made of successive blocks of pilot symbols, preferably using pilot symbol blocks that both precede and follow the data symbols in the frame being processed. The channel impulse response estimates for blocks of pilot symbols are buffered and used by an interpolator to determine an interpolated channel impulse response estimate for each data symbol as a function of both the pilot symbols and of predefined channel characteristics. The interpolated channel impulse response estimates are applied to successive data symbols in the delayed data signal, enabling the data to be decoded, compensating for fading and interference. Interpolation using predefined channel characteristics based on worst case conditions substantially improves the bit error rate (BER) for the data recovered, compared to the prior art.

Compensation for multi-path interference using pilot symbols

A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal. By frequency shifting the filtered signal (either up or down) to a center frequency of approximately 1,700 Hz, interference between positive and negative frequencies is substantially eliminated. A digital-to-analog converter (DAC) (74) produces an analog FSK modulated signal. At a receiving modem (29), the demodulator digitizes the FSK modulated signal at a 19.2 KHz sample rate and shifts the digitized modulated signal to a center frequency of 0 Hz, producing a complex baseband comprising in-phase (real) and quadrature (imaginary) components. The DSP determines the instantaneous phase of the complex baseband signal, and from the time derivative of the instantaneous phase, determines its frequency. The instantaneous frequency is interpolated at eight times the major sample rate, producing an interpolated frequency signal so that changes in the sign of the interpolated frequency can be used to determine the logic level and zero crossing of the demodulated signal with greater resolution, substantially reducing jitter. Correlation of the demodulated signal at the data rate further reduces jitter.

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Burnaby, Canada

Robert F Marchetto