Intel Corporation

Hewlett-packard Development Company, L.p.

Robert F Krick

Chan W Lee

Alan Beecher Kyker

Per H Hammarlund

Hitesh Ahuja

Joseph F Rohlman

William Alexander

Glenn J Hinton

Reynold V D'Sa

Roshan J Fernando

David J Sager

Michael D Upton

Amar A Ghori

Rebecca E Hebda

Paul L Rogers

Adalberto Golbert

Richard A Weier

Duane A Wiens

Keng L Wong

Darrell D Boggs

Douglas M Carmean

Vipul Gandhi

David Jerome Johnson

Peter J DesRosier

Slade A Morgan

Anurag Sah

Kathakali Debnath

Douglas M Carean

Milind Mittal

Yoav Hochberg

A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

LRU cache replacement for a partitioned set associative cache

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

System and method for storing immediate data

The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.

Detection, recovery and prevention of bogus branches

A buffer mechanism for buffering microinstructions between a trace cache and an allocator performs a compacting operation by overwriting entries within a queue, known not to store valid instructions or data, with valid instructions or data. Following a write operation to a queue included within the buffer mechanism, pointer logic determines whether the entries to which instructions or data have been written include the valid data or instructions. If an entry is shown to be invalid, the write pointer is not advanced past the relevant entry. In this way, an immediately following write operation will overwrite the invalid data or instruction with data or instruction. The overwriting instruction or data will again be subject to scrutiny (e.g., a qualitative determination) to determine whether it is valid or invalid, and will only be retained within the queue if valid.

Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue

A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.

Multiple cache coherency

A method of operating a cache comprises the steps of reading first information from a tag memory for at least two cache lines; reading second information from the tag memory for at least two cache lines; writing third information to the tag memory updating the first information; comparing (i) an address of the tag memory associated with the step of reading the second information with (ii) an address of the tag memory associated with the step of writing the third information and, in response, selectively replacing the second information with the third information; and writing, after the step of comparing, fourth information to the tag memory updating the second information.

System for and method of operating a cache

A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.

System of and method for flow control within a tag pipeline

The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if the same memory location is accessed. If the same memory location is affected, a dependency is created which ensures the youngest queue entry which is present at the time the check is made occurs before the present outstanding request.

Fast priority determination circuit with rotating priority

An exemplary processor or trace cache according to the present invention includes a cache unit, which includes a data array that stores traces. The processor or trace cache also includes a control block connected to the cache unit, the control block unrolling loops when building the traces. In one exemplary method of unrolling loops, the processor or trace cache unrolls loops until the trace is a minimum length. In another exemplary embodiment, the processor or trace cache unrolls only those loops in which the head of the loop is the trace head. In a third exemplary embodiment, the processor or trace cache unrolls loops based on a predicted number of iterations of the loop when executed.

System and method for unrolling loops in a trace cache

A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested address to reduce the amount of data that must be read. Mini-tag read and compare operations may be performed in parallel to a full tag read operation, and a data read operation of only the data identified by a matching mini-tag may be performed in parallel to a full tag compare operation. A victim selection method for writing data into the trace cache is used to maintain the uniqueness of the mini-tags.

Multi-tag system and method for cache read/write

A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.

Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table

Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

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Beaverton, OR, United States of America

Robert F Krick