Intel Corporation

Robert F Hainsey

Bernie B Hu

Jeffrey G Lewis

Robert S Chau

Giang T Dao

Leopoldo D Yau

Shahriar S Ahmed

Chan-Hong Chern

Robert J Stoner

Todd E Wilke

A method and apparatus for printing vertically and horizontally aligned features having reduced, substantially equal, critical dimensions on a photoresist-coated semiconductor wafer are disclosed. Radiant energy is passed through a pattern transfer tool to irradiate a first region of the wafer when the wafer is at a first position relative to the pattern transfer tool. The wafer is then positioned at a second position relative to the pattern transfer tool offset from the first position by a first distance along an axis aligned with the horizontal features and by a second distance along an axis aligned with the vertical features. The second distance is different from the first distance by a compensation distance. Radiant energy is then passed through the pattern transfer tool to irradiate a second region of the wafer region defining a second side of each of the horizontally and vertically aligned features.

Reducing the critical dimension difference of features printed on a substrate

Method and apparatus for reducing the critical dimension difference of

An attenuated phase-shifted reticle is disclosed. The reticle comprises a device region and a scribeline region. The scribeline region further comprises metrology cells, which contain features to be patterned for the purpose of measurement, etc. Other portions of the scribeline region comprise a sub-resolution pattern of, for example, lines and spaces 180.degree. out of phase. Since the pattern is sub-resolution, it will not print. Since the pattern comprises features 180.degree. out of phase, the intensity of radiation underneath the pattern is significantly reduced. Therefore, in a lithography method incorporating multiple exposures of the scribeline region, the metrology cells are not overexposed by the overlapping exposures in the stepping system.

Phase-shifted opaquing ring

A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

Inverted spacer transistor

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Portland, OR, United States of America

Robert F Hainsey