North Carolina State University

The United States of America As Represented by the Secretary of

Lumenz, Inc.

United States of America As Represented by the Secretary of the Air Force

Carnegie Mellon University

Cree Research Inc.

Robert F Davis

Thomas Gehrke

Kevin J Linthicum

Darren B Thomson

Tsvetanka Zheleva

Pradeep Rajagopal

Ok-hyun Nam

Eric Porter Carlson

Hua-shuang Kong

Jeffrey T Glass

Scott A Smith

Michael D Bremser

John Adam Edmond

John Williams Palmour

Calvin H Carter, Jr

Bunmi T Adekore

William A Bruce

Patrick T Lum

Roy E Bry

Helen C Su

Lisa S Porter

Robert C Glass

Kieran M Tracy

Jonathan M Pierce

Cheng C Wang

Charles Eric Hunter

George B Kenney

Duane Finello

Scott L Roberson

Jacob H Melby

Jason Gu

Ok-Hyun Nam

Sensors for sensing/measuring one or more analytes in a chemical environment. Each sensor is based on a semiconductor structure having an interfacial region containing a two-dimensional electron gas (2DEG). A catalyst reactive to the analyte(s) is in contact with the semiconductor structure. Particles stripped from the analyte(s) by the catalyst passivate the surface of the semiconductor structure at the interface between the catalyst and the structure, thereby causing the charge density in the 2DEG proximate the catalyst to change. When this basic structure is incorporated into an electronic device, such as a high-electron-mobility transistor (HEMT) or a Schottky diode, the change in charge density manifests into a change in an electrical response of the device. For example, in an HEMT, the change in charge density manifests as a change in current through the transistor, and, in a Schottky diode, the change in charge density manifests as a change in capacitance.

Two-dimensional electron gas (2DEG)-based chemical sensors

A p-type ZnO-based II-VI compound semiconductor layer has silver, potassium and/or gold dopants therein at a net p-type dopant concentration of greater than about 1&#xd7;10cm. A method of forming the layer includes using an atomic layer deposition (ALD) technique. This technique includes exposing a substrate to a combination of gases: a first reaction gas containing zinc at a concentration that is repeatedly transitioned between at least two concentration levels during a processing time interval, a second reaction gas containing oxygen and a p-type dopant gas containing at least one p-type dopant species selected from a group consisting of silver, potassium and gold. A concentration of oxygen in the second reaction gas may also be repeatedly transitioned between at least two concentration levels. The concentration of zinc in the first reaction gas and the concentration of oxygen in the second reaction gas may be transitioned in an alternating sequence, so that relatively high zinc concentrations in the first reaction gas overlap with relatively low oxygen concentrations in the second reaction gas and vice versa.

Methods of forming zinc oxide based II-VI compound semiconductor layers with shallow acceptor conductivities

A method of preparing an n-type epitaxial layer of aluminum nitride conductively doped with germanium comprises directing a molecular beam of aluminum atoms onto the growth surface of a substrate that provides an acceptable lattice match for aluminum nitride; directing a molecular beam of activated nitrogen to the growth surface of the substrate; and directing a molecular beam of germanium to the growth surface of the substrate; while maintaining the growth surface of the substrate at a temperature high enough to provide the surface mobility and sticking coefficient required for epitaxial growth, but lower than the temperature at which the surface would decompose or the epitaxial layer disassociate back into atomic or molecular species.

Germanium doped n-type aluminum nitride epitaxial layers

An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer. The lateral growth from the sidewalls of the posts may be continued so that the gallium nitride layer grows vertically through the openings in the mask and laterally overgrows onto the mask on the tops of the posts, to thereby form a gallium nitride semiconductor layer. The lateral overgrowth can be continued until the grown sidewalls coalesce on the mask to thereby form a continuous gallium nitride semiconductor layer. Microelectronic devices may be formed in the continuous gallium nitride semiconductor layer.

Pendeoepitaxial gallium nitride semiconductor layers on silicon carbide substrates

More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench. Embodiments of gallium nitride semiconductor structures according to the present invention can include a sapphire substrate and an underlying gallium nitride layer on the sapphire substrate. The underlying gallium nitride layer includes therein at least one post and at least one trench. The at least one post each includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a sapphire floor. A lateral gallium nitride layer extends laterally from the gallium nitride sidewall of the at least one post into the at least one trench. In a preferred embodiment, the at least one trench extends into the sapphire substrate such that the at least one post each includes a gallium nitride top, a gallium nitride sidewall and a sapphire sidewall and the at least one trench includes a sapphire floor. The sapphire floor preferably is free of a vertical gallium nitride layer thereon and the sapphire sidewall height to sapphire floor width ratio preferably exceeds about 1/4. A mask may be included on the sapphire floor and an aluminum nitride buffer layer also may be included between the sapphire substrate and the underlying gallium nitride layer. A mask also may be included on the gallium nitride top.

Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates, and gallium nitride semiconductor structures fabricated thereby

A gallium nitride layer is laterally grown into a trench in the gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. At least one microelectronic device may then be formed in the lateral gallium nitride semiconductor layer. Dislocation defects do not significantly propagate laterally into the lateral gallium nitride semiconductor layer, so that the lateral gallium nitride semiconductor layer is relatively defect free.

Methods of fabricating gallium nitride semiconductor layers by lateral growth into trenches

A substrate includes non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops and the trenches include non-gallium floors. Gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops. Preferably, gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium nitride pyramids. The gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature. The first temperature preferably is about 1000&#xb0; C. or less and the second temperature preferably is about 1100&#xb0; C. or more. However, other than temperature, the same processing conditions preferably are used for both growth steps. The grown gallium nitride on the pyramids preferably coalesces to form a continuous gallium nitride layer. Accordingly, gallium nitride may be grown without the need to form masks during the gallium nitride growth process. Moreover, the gallium nitride growth may be performed using the same processing conditions other than temperatures changes. Accordingly, uninterrupted gallium nitride growth may be performed.

Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby

Second gallium nitride layers that extend into trenches in first gallium nitride layers

Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts

More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench. Embodiments of gallium nitride semiconductor structures according to the present invention can include a sapphire substrate and an underlying gallium nitride layer on the sapphire substrate. The underlying gallium nitride layer includes therein at least one post and at least one trench. The at least one post each includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a sapphire floor. A lateral gallium nitride layer extends laterally from the gallium nitride sidewall of the at least one post into the at least one trench. In a preferred embodiment, the at least one trench extends into the sapphire substrate such that the at least one post each includes a gallium nitride top, a gallium nitride sidewall and a sapphire sidewall and the at least one trench includes a sapphire floor. The sapphire floor preferably is free of a vertical gallium nitride layer thereon and the sapphire sidewall height to sapphire floor width ratio preferably exceeds about &frac14;. A mask may be included on the sapphire floor and an aluminum nitride buffer layer also may be included between the sapphire substrate and the underlying gallium nitride layer. A mask also may be included on the gallium nitride top. The mask on the floor and the mask on the top preferably comprise same material.

A substrate includes non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops and the trenches include non-gallium floors. Gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops. Preferably, gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium nitride pyramids. The gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature. The first temperature preferably is about 1000&deg; C. or less and the second temperature preferably is about 1100&deg; C. or more. However, other than temperature, the same processing conditions preferably are used for both growth steps. The grown gallium nitride on the pyramids preferably coalesces to form a continuous gallium nitride layer. Accordingly, gallium nitride may be grown without the need to form masks during the gallium nitride growth process. Moreover, the gallium nitride growth may be performed using the same processing conditions other than temperatures changes. Accordingly, uninterrupted gallium nitride growth may be performed.

A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer. The first overgrown layer is then masked with the second mask that includes a second array of openings therein. The second array of openings is laterally offset from the first array of openings. The first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.

Gallium nitride semiconductor structure including laterally offset patterned layers

A gallium nitride microelectronic layer is fabricated by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer. The silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide, or the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate, or the (111) silicon layer is a portion of a Silicon-On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate.

Methods of fabricating gallium nitride microelectronic layers on silicon layers

A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.

Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth

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Raleigh, NC, United States of America

Robert F Davis