International Business Machines Corporation

Robert F Cook

Eric Gerhard Liniger

Ronald Lee Mendelson

Stephen Edward Greco

Donald W Brouillette

Vincent James McGahay

Wayne John Howell

Thomas George Ference

Kamalesh K Srivastava

John Patrick Hummel

Rebecca D Mih

Joyce C Liu

James L Hedrick

Robert Dennis Miller

Craig Jon Hawker

Willi Volksen

Nancy Anne Greco

Kenneth Raymond Carter

Ernest N Levine

Do Yeung Yoon

John M Blondin

Martha Alyne Harbison

Eduardo Garcia

David Frederick Diefenderfer

Victor Yee-Way Lee

Richard Charles Whiteside

Dean R Sanders

Sung-Mog Kim

A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Method and system for dicing wafers, and semiconductor structures incorporating the products thereof

A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.

Semiconductor structure and package including a chip having chamfered edges

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

Interim oxidation of silsesquioxane dielectric for dual damascene process

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

In situ formation of protective layer on silsesquioxane dielectric for dual damascene process

A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.

Mechanical strength die sorting

The invention relates to a process for making an integrated circuit device comprising (i) a substrate, (ii) metallic circuit lines positioned on the substrate, and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the condensation product of silsesquioxane in the presence of a photosensitive or thermally sensitive base generator.

Process for manufacture of integrated circuit device

The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.

Method for producing a crack stop for interlevel dielectric layers

A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information

Integrated circuit having crack stop for interlevel dielectric layers

A serpentine pattern has been found to be effective at interrupting propagation of delamination cracks in thin film layers. The ring is provided on a semiconductor chip to suppress crack propagation from the chip edge. The ring is effective even though it is filled with metal, the serpentine pattern providing significantly increased area as compared with a standard linear crack stop that the energy for crack propagation is dissipated. In addition to serpentines, pattern features such as staggered filled ring patterns and connected rings will also be effective at reducing the propagation of delamination cracks from edge to active area by virtue of the increased area of interaction between the crack and the crack stop.

Chip crack stop

The invention relates to a process for making an integrated circuit device comprising (I) a substrate, (ii) metallic circuit lines positioned on the substrate, and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the condensation product of silsesquioxane precursor in the presence of an organic amine having a boiling point greater than 150.degree. C.

Method and apparatus for preventing chip breakage during semiconductor

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Putnam Valley, NY, United States of America

Robert F Cook