Transmeta Corporation

Other

Robert F Cmelik

Malcolm J Wing

Edmund Joseph Kelly

Guillermo Juan Rozas

David A Dunn

David Pardo Keppel

Robert Bedichek

David Roger Ditzel

Grzegorz B Zyner

Douglas A Laird

Colin B Hunter

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Translated memory protection apparatus for an advanced microprocessor

Translated memory protection

A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a branch instruction to before the branch instruction, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instruction in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically-detected and handled precisely.

Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register

A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a branch instruction to before the branch instruction, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instruction in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically detected and handled precisely.

Exception handling with inserted status check command accommodating floating point instruction forward move across branch

A process which automatically inserts commands that test for raised exceptions indicating floating point status exceptions into a sequence of instructions to be executed, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instructions in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically detected.

Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state

A process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.

Method and apparatus for accelerating fault handling

A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

Method and apparatus for maintaining context while executing translated instructions

A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.

Combining hardware and software to provide an improved microprocessor

A memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures.

Growing community of inventors

Sunnyvale, CA, United States of America

Robert F Cmelik