Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Sandisk Technologies Inc.

Robert Eugeniu Mateescu

Cyril Guyot

Zvonimir Z Bandic

Luiz M Franca-Neto

Qingbo Wang

Dejan Vucinic

Lluis Pamies-Juarez

Minghai Qin

Seung-Hwan Song

Yongjune Kim

Hessam Mahdavifar

Kiran Kumar Gunnam

Frank R Chu

Chao Sun

Timothy Tsai

Ivana Djurdjevic

Shad Henry Thorstenson

Tomohiro Harayama

Koen De Keyser

Adam Manzanares

Yuval Cassuto

Mark Christiaens

Filip Blagojevic

Arman Fazeli Chaghooshi

A storage device minimizes redundancy for stuck bit codes when writing a message to a memory device. A controller generates a set of masks that are codewords and that include values that correspond to stuck bit values. The set of masks may include full length codewords or shortened codewords. When the controller receives a message including a predefined number of label bits and determines that a location in the memory device where the message is be stored includes two stuck bits, the controller encodes the message to produce a first message codeword. The controller then locates a mask from the set of masks, wherein when the mask is added to the first message codeword, any two stuck message bits are masked. The controller computes a final message codeword using the first message codeword and the mask and stores the final message codeword on the memory device.

Minimizing redundancy for stuck bit coding

A storage device processes storage-free stuck bits information when writing and reading stored on the memory device. A controller encodes the data with cyclic error-correcting codes to generate a codeword and determines that a location in the memory device where codeword is be stored includes a stuck bit. Rather than storing the stuck bits information, when storing the codeword, the controller generates an encoding mask, adds the encoding mask to the codeword to generate encoded data, and stores the encoded data on the memory device. When reading the encoded data, the controller generates a list of decoding masks including the encoding mask, goes through the lists and adds a decoding mask to the encoded data. The controller decodes the encoded data with the encoding mask from the list and returns the data.

Stuck bits encoding and decoding on a storage device

A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Computational resource allocation in ensemble machine learning systems

The disclosed technology can advantageously provide an efficient data recovery system including a plurality of storage nodes including a first storage node and a second storage node, and a storage logic that is coupled to the storage nodes and that manages storage of data on the storage nodes. The storage logic is executable to: receive a data set including data elements including a first set of data elements associated with the first storage node and a second set of data elements associated with the second storage node; generate a first parity of the data set, the first parity including a horizontal parity including a set of horizontal parity entries; and combine the data elements from the data set to produce a skipper parity including a set of skipper parity entries. Combining the data elements includes transforming a subset of the data elements from the data set using an invertible operation, the set of horizontal parity entries being different from the set of skipper parity entries.

Data recovery and regeneration using parity code

The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

Cell-level realization of burn after reading for NAND flash

In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.

Data mapping enabling fast read multi-level 3D NAND to improve lifetime capacity

Technology is provided for updating a data set at a data storage system. In an example storage system, the system stores a data set in a plurality of data storage devices. The system stores parity data at a plurality of parity devices. The system receives update data from a client system for a first section of the data set. The system generates updated parity data based on an original version of the first section of the data set and the update data. The system transmits update parity data to the plurality of parity devices. The system receives update notifications from a plurality of parity devices. The system determines that update notifications have been received from at least a threshold number of parity devices in the plurality of parity devices. In response, the system updates the first section of the data set at the leader data storage device.

Update efficient consensus protocols for erasure coded data stores

Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

System and methodology for low latency error management within a shared non-volatile memory architecture

Technology is described for performing wear leveling in non-volatile storage. Mapping from logical addresses to intermediate addresses may be performed without the use of a mapping table having an entry for each page. Intermediate addresses may be mapped to physical addresses in a physical address space partitioned into a number of buckets. Wear-leveling may be performed within each bucket by, for example, rotating data within a bucket. The bucket size and rotation rate may be selected to keep wear on the memory cells well with tolerance. The mapping from logical addresses to intermediate addresses may periodically be changed, with an associated move of data from one bucket to another bucket to provide additional wear leveling.

Wear leveling in non-volatile storage

The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.

Bad page and bad block management in memory

Techniques for generating parities and repairing data erasures using a cache oblivious encoding algorithm are disclosed. The system includes an encoding module which receives a request to recreate data for a subset of a plurality of content stores from a storage manager. The encoding module generates a new first parity and a new second parity using the remaining content in the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second parity for the plurality of content stores. The encoding module may recreate the data for the plurality of content stores using the first portion of the requested data and the second portion of the requested data.

Cache oblivious algorithm for butterfly code

A system that implements a near-optimal, reduced-dependency erasure code construction to redundantly distribute computer data across multiple storage nodes includes a memory that stores machine instructions and a processor that executes the machine instructions to group storage segments into discrete groups, each of which corresponds to an individual storage node. The processor further executes the machine instructions to represent regeneration constraints and associate the constraints with storage segments in multiple storage nodes. The processor also executes the machine instructions to generate a parity check matrix based on the regeneration constraints, the associations and the storage segments. The processor additionally executes the machine instructions to construct a generator matrix based on the parity check matrix.

Distributed data storage with reduced storage overhead using reduced-dependency erasure codes

A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.

Storing parity data separate from protected data

Small objects are efficiently stored with erasure codes by combining a small object with other small objects and/or large objects to form a single large object for chunking, and providing early notification of permanent storage to the sources of the objects to prevent small objects from becoming stale while waiting for additional objects to be combined.

Storage cluster and method that efficiently store small objects with erasure codes

Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Growing community of inventors

San Jose, CA, United States of America

Robert Eugeniu Mateescu