Infineon Technologies Ag

Robert Esterl

Zoltan Manyoki

Heinz H&ouml;nigschmid

Thomas R&ouml;hr

Helmut Kandolf

Georg Braun

Stefan Lammers

Thomas B&ouml;hm

Tobias Schlager

The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits

An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

Integrated semiconductor memory having memory cells with a ferroelectric memory property

A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to the inputs. Second electrodes of the pumping capacitors are in each case connected via a first circuit module to a supply potential (ground) and via a second circuit module to the output. Also present is a controllable short-circuiting element, the controllable path of which is disposed between the second electrodes of the two pumping capacitors.

Charge pump with charge equalization for improved efficiency

A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the &ldquo;pulsed plate concept&rdquo;. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

Method for operating an integrated memory

A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

CMOS voltage divider

The memory has a control unit, which, in order to generate a common reference potential on the two bit lines, turns on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turns off the selection transistors, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.

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München, Germany

Robert Esterl