Freescale Semiconductor,inc.

Koninklijke Philips Corporation N.V.

Motorola Corporation

Robert Elliott Boone

Kevin Dean Lucas

Edward Outlaw Travis, Jr

Ruiqi Tian

Puneet Sharma

Tat-Kwan Edgar Yu

Aykut Dengi

Alfred J Reich

Sejal N Chheda

Matthew A Thompson

James Edward Vasek

William Louis Wilkinson

Christophe Couderc

Yves Rody

Mark S Roberton

A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.

Method for analyzing placement context sensitivity of standard cells

Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.

Method and apparatus for designing an integrated circuit using inverse lithography technology

Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.

Method and apparatus for designing and integrated circuit

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Method for adding features to a design layout and process for designing a mask

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Austin, TX, United States of America

Robert Elliott Boone