Lexar Media, Inc.

Xilinx, Inc.

Xilnix, Inc.

Robert Edwin Payne

Peter John Smith

Alan Welsh Sinclair

Graham Johnston

In one embodiment, a shift register is provided. The LFSR includes a plurality of processing stages coupled in series, each configured to implement N taps of the LFSR. N single-tap circuits are coupled together in series and arranged to implement the last N taps of the LFSR. Each coefficient(s) of a feedback polynomial of the LFSR is implemented by one of the taps of the plurality of processing stages or the N single-tap circuits. A feedback generation circuit is configured to provide, for each of the plurality of processing stages, a respective feedback signal as a function of polynomial coefficients implemented by the processing stage and output from one or more of the N single tap circuits.

Shift register having multiple processing stages

In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask.

Multi-stage forward error correction decoding

Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption.

Power management of non-volatile memory systems

According to one embodiment of the present invention, there is provided a power management system for use in a computer system having a memory system incorporating a non-volatile memory and a controller which presents the logical characteristics of a disc storage device to a host, the power management system comprising means for monitoring the operational activity levels within at least some of the components of the controller and arranged, in response to the monitored levels, to vary the power consumed by selected components of the controller.

Power management system

In one embodiment of the present invention, there is disclosed, a method of handling data which is being written to and stored in flash memory, wherein input data, comprising information data and overhead data, undergoes a reversible transformation before being written to flash memory whereupon each bit stored in flash memory, as flash data, is a function of both information data and header data.

Data handling system

According to a first aspect of the present invention, there is provided a memory system having a controller and a non-volatile memory storing firmware for start up and for normal operation of the system, the controller comprising, a volatile memory; and a processor; wherein the controller is arranged to operate during initialization or configuration of the system so that the start up firmware stored in the non-volatile memory is loaded into the volatile memory under hardware control by the controller and with the processor halted, the start up firmware in the volatile memory being subsequently executed by the processor.

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Edinburgh, United Kingdom

Robert Edwin Payne