Motorola Corporation

Robert Edwin Jones, Jr

Bruce E White

Papu D Maniar

Bradley M Melnick

Reza Moazzami

Andrew C Campbell

Hideo Oi

A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (,through,). The region (,) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (,). This plug (,) forms a storage node region for a DRAM and electrically contacts to a current electrode (,) of a DRAM pass transistor. Opening (,) is filled concurrently with the filling of opening (,), to form a metallic plug (,) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (,) is filled concurrent with regions (,and,) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (,) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (,through,) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

Method for forming a capacitor electrode

A first etch stop layer (,) is formed over a semiconductor substrate (,). A first dielectric layer (,) is formed over the first etch stop layer (,). An opening (,) is formed in the first dielectric layer (,). The opening (,) extends through the first dielectric layer (,) and exposes a first conductive material (,) under the first dielectric layer (,). A second conductive material (,) is deposited over the semiconductor substrate (,) and within the opening (,). The second conductive material (,) electrically contacts the first conductive material (,). Portions of the second conductive material (,) lying outside of the opening (,) are removed and then portions of the first dielectric layer (,) are removed to expose portions of the first etch stop layer (,).

Method for forming a semiconductor device using an etch stop layer

A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

Method for forming semiconductor device including a dual inlaid structure

A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

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Austin, TX, United States of America

Robert Edwin Jones, Jr