International Business Machines Corporation

Other

Globalfoundries Inc.

Robert Edward Galbraith

Adrian Cuenin Gerhard

Daniel Frank Moertl

Rick A Weckwerth

Brian Eric Bakke

Joseph R Edwards

Gowrisankar Radhakrishnan

Carl E Forhan

Damir Anthony Jamsek

William J Maitland, Jr

Steven Paul Norgaard

Timothy James Larson

Jessica M Gisi

Timothy J Schimke

Andrew Kenneth Martin

Murali N Iyer

Kenneth J Oakes

Donald J Ziebarth

Roman Alexander Pletka

Charalampos Pozidis

Leslie W Wyman

Brian L Bowles

Brian James King

Matthew Szekely

Evangelos Stavros Eleftheriou

Andrew Dale Walls

Ioannis Koltsidas

Robert Haas

Steven G Glassen

Mark A Johnson

Ellen Marie Bauman

Allan Samuel Meritt

Roger E Hough

Michael Joseph Carnevale

Marten J Halma

Xiao-yu Hu

Kenneth J Fredericks

David E Stucki

Paul Gary Reuland

Frederic Lawrence Huss

Mark J Moran

Jeremy T Ekman

Scott Alan Bauman

Gerald Mark Grabowski

Suzanne M John

Mussie T Negussie

Abby Harrison

Dennis David Reetz

Harry M Yudenfriend

Nikolaos Papandreou

Thomas Mittelholzer

Karl Allen Nielsen

Timothy J Fisher

Charles John Camp

Milos Stanisavljevic

Thomas Edward Cook

David Ray Kahler

Joseph C Elliott

Kevin E Sallese

Michael Steven Faunce

Martin W Sachs

Stephen M Tee

Christopher M Dennett

Francis Gassert

Richard Roland Guyette

Martin Taubert

Frank W Brice

Joseph Thomas Writz

Mark J Fantacone

Assaf Marron

Dennis Carl Mairet

John C Rathjen, Jr

James C Mazurowski

Russell Paul VanDuine

Michael J Anderson

Michael T Roble

Laurel Scaife

Paul A Malinowski

Daniel F Moerti

Lawrence P Connoy

Mark Yadlosky

Jana Christine Migge

Dylan R Gransee

Ethan J Johnson

Austin J Mackedanz

Shannon C Strutz

Douglas David Prigge

Embodiments of the present disclosure provide systems and methods for implementing enhanced Device Control Block (DCB) scan recovery for channel recovery actions. A disclosed method comprises identifying channels to be recovered and creating a DCB bit array reflecting each DCB to be scanned for the set of the channels to be recovered by a system assist processor. The system assist processor performs asynchronous channel communication area (CCA) recovery processing, starts synchronous DCB scan recovery, and sequentially processes an incremental portion of the DCB bit array interleaved with asynchronous CCA recovery processing. The system assist processor completes asynchronous CCA recovery processing and synchronous DCB scan recovery to complete channel recovery of the set of channels. The system assist processor starts each channel of the set of channels responsive to completing channel recovery processing for each channel.

Device control block scan for channel recovery actions

A product, system, and/or method of managing memory media where in response to determining that a memory system is low on one or more RTU Block Stripes needed to form a ready-to-use (RTU) Block Stripe set, one or more determined Die #/Plane # combinations low on one or more RTU Block Stripes needed to form a RTU Block Stripe Set are identified, wherein all Blocks in a RTU Block Stripe and all Block Stripes in each RTU Block Stripe Set have been subject to a removal and erasure process and one or more Blocks to undergo the removal process in the identified one or more determined Die #/Plane # combinations to create one or more RTU Block Stripes needed to form a RTU Block Stripe Set are prioritized.

Management of flash storage media

Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

Host request pacing to balance resources and throughput

Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Flash memory garbage collection

A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die #and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane #combinations; and prioritizing in the one or more determined Die #/Plane #combinations one or more memory media Blocks for the removal and/or erasure process.

A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Logical to virtual and virtual to physical translation in storage class memory

A method and system of managing memory, the method including receiving a request for storage space in the memory system; obtaining a timestamp for a new Logical Unit Number (LUN); allocating a range of logical blocks to the new LUN in accordance with its requested size, the range of logical blocks including a starting logical block and a number of blocks; assigning the timestamp to the new LUN as the LUN creation timestamp; and saving the LUN creation timestamp with other metadata identifying the new LUN and the allocated logical blocks. Methods and system for deleting LUNs and using a deletion timestamp are disclosed as is a process to format a LUN.

Logical memory allocation and provisioning using timestamps

In an approach to NV SCM data flow with mismatched block sizes, responsive to receiving a command from a host on a memory controller for a storage class memory, whether the command is a write command is determined. Responsive to determining that the command is the write command, the command is inserted into a first buffer. Responsive to the command exiting the first buffer, whether the command generates a cache hit from the internal cache is determined. Responsive to determining that the command generates the cache hit, the write data is written into the internal cache. Responsive to determining that the command does not generate the cache hit, whether an oldest page in the internal cache is dirty is determined. Responsive to determining that the oldest page in the internal cache is dirty, a modified oldest page is written to the internal cache and a second buffer.

Non-volatile storage class memory data flow with mismatched block sizes

In an approach to failed media channel recovery throttling, responsive to detecting a programming error on an addressable unit during programming of a block stripe, the block stripe is placed on a recovery/data migration queue. An error counter for the addressable unit on which the programming error occurred is incremented. The block stripes from the recovery/data migration queue are built excluding a specific channel containing the addressable unit on which the programming error occurred. Responsive to determining that the queue for the recovery/data migration is empty, building the block stripes resumes using the plurality of channels, where the specific channel containing the addressable unit on which the programming error occurred is included. Responsive to determining that a number of errors on a specific addressable unit exceeds a predetermined threshold based on the error counter for the specific addressable unit, the specific addressable unit is decommissioned.

Failed media channel recovery throttling

A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Scrub management in storage class memory

A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.

Virtual to physical translation and media repair in storage class memory

Techniques for persisting a logical address-to-virtual address table in a solid state storage device are presented. An example method includes receiving a request to write data to a logical block address (LBA) in a memory component of the solid state storage device. The data is written to a location identified by a virtual block address (VBA) in the solid state storage device. The VBA is stored in a rotating dump table in a reserved logical unit of the solid state storage device. A mapping between the LBA and the VBA is stored in a rotating journal table located in the reserved logical unit. The rotating journal table is buffered such that a number of journal entries are stored in a buffer until a threshold number of journal entries are committed to the rotating journal table. A pointer to a current address in the rotating journal is stored in the buffer.

Persistent logical to virtual table

Examples of techniques for a thread checkpoint table for a computer processor are described herein. An aspect includes, based on detecting an early power-off warning (EPOW) signal, determine, based on a thread checkpoint table, whether a status of a thread of a processor indicates that the thread has begun a unit of atomic work. Another aspect includes, based on determining that the status of the thread of the processor indicates that the thread has begun the unit of atomic work, allowing the thread to continue execution of the unit of atomic work. Another aspect includes determining, based the status of the thread in the thread checkpoint table, that the thread has completed the unit of atomic work. Another aspect includes, based on determining that the thread has completed the unit of atomic work, suspending the thread.

Thread checkpoint table for computer processor

An apparatus may include a redundant array of independent disks (RAID) array including a plurality of solid state drives (SSDs). The apparatus may further include a RAID array controller coupled to the plurality of SSDs. The RAID array controller may be configured to determine whether one or more logical block addresses (LBAs) of a stripe of the RAID array are unmapped. The one or more LBAs may be associated with one or more SSDs of the plurality of SSDs. The RAID array controller may be configured to determine data corresponding to the stripe based on the determination of whether the one or more LBAs are unmapped. RAID operations (such has Rebuild, Exposed Mode Read, and/or Parity Resync operations) may be optimized based on the knowledge of which LBAs are mapped and unmapped.

Raid array systems and operations using mapping information

Growing community of inventors

Rochester, MN, United States of America

Robert Edward Galbraith