International Business Machines Corporation

Robert Earl Medlin

Gregg Steven Lucas

Craig Anthony Klein

Gary William Batchelor

Katherine Tyldesley Blinick

Juan Antonio Yanes

Michael L Harper

Carl Evan Jones

Michael T Benhase

Joseph S Hyde, Ii

Forrest Lee Wade

Russell Lee Ellison

Belayneh Tafesse

Mary Anne J Marquez

Mary A J Marquez

John Charles Elliott

Brent Cameron Beardsley

Yutaka Kawai

Enrique Q Garcia

Shah Mohammad Rezaul Islam

Kenneth Robert Schneebeli

Tohru Sumiyoshi

Michael Allen Curnalia

Jack Harvey Derenburger

Rezaul Shah Mohammad Islam

Yvonne Hanson Kleppel

Gordon Leon Washburn

Michael H Stamps

Dell Patrick Leabo

Bryan N Cardwell

Rajendrasinh Banesinh Jadeja

A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.

Firehose dump of SRAM write cache data to non-volatile memory using a supercap

Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream.

Systems and methods for monitoring high speed network traffic via sequentially multiplexed data streams

A method for automatically detecting and correcting one or more hang conditions within one or more of a master device and target device of a serial bus interface when one or more signals are held in an invalid state. A hang timer monitors one or more operations of the serial bus when the serial bus is participating in a serial bus transfer. If the transfer does not end before the bus timeout value has been exceeded, the hang timer will issue a reset to the state machine forcing the state machine back to an idle state. The hang timer will also disable the serial bus drivers of the state machine, whereby the hang condition is corrected.

Freeing a serial bus hang condition by utilizing distributed hang timers

A high speed fabric is provided and is partitioned into sub-fabrics for host adapter traffic and device adapter traffic. A high-speed switch includes an expander for host adapter traffic and an expander for device adapter traffic. The high-speed switch also includes a plurality of connectors, where each connector is partitioned into dual interfaces. For each connector, one interface is connected to the host adapter traffic expander and the other interface is connected to the device adapter traffic expander. Blades are provided with one or more connectors, where each connector is partitioned into dual interfaces for host adapter traffic and device adapter traffic. The blades may be any combination of processor blades, boot drive enclosure blades, switched bunch of disks enclosure blades, and/or integrated RAID controller disk enclosure blades.

Independent drive enclosure blades in a blade server system with low cost high speed switch modules

Because cable length affects signal quality, amplifying signals differently to account for cable length ('tuning') becomes especially important when high speed signals are used. Cable length information may be stored in a non-volatile memory which may be integrated into a cable assembly or may be a discrete component between the cable and an interface. Rather than using a dedicated data line to the memory component a ground line may be connected to the memory component and multiplexed. During normal operation the selected line is grounded through a switching device. When a cable is detected, a management controller changes the state of the switching device to decouple the selected line from ground to allow the management controller access to the data stored in the memory component, including cable length information. The selected line is then re-coupled to ground and interface circuits may be tuned for the cable length.

Multiplexing a ground signal on a high speed cable interface to provide access to cable vital product data

An apparatus, system, and method are disclosed for integrating redundant array of independent disk ('RAID') storage within a blade center. A plurality of mutually autonomous storage subsystems mount within the blade center through a switch. Each storage subsystem includes a storage module comprising a plurality of storage devices and a RAID controller. A server blade mounted within the blade center may access a first storage subsystem through a switch module. The switch module is a non-blocking, cross-point switch. In one embodiment, the switch module restricts the server blade's access to a second storage subsystem.

Apparatus, system, and method for integrating multiple raid storage instances within a blade center

An apparatus is provided and includes a label layer, disposed in a user visible interface of a front bezel, in which an icon is etched, a multi-layer printed circuit board (PCB), abutting a rear surface of the label layer and being configured to form a light source housing that positionally corresponds to that of the icon, a light source assembly, including a substrate, which is fixedly recessed in a rear portion of the light source housing, and a light emitting portion, supported by the substrate, from which light is emitted toward at least the icon, and solder plating to reflect light emitted by the light source away from the preselected icon toward the preselected icon.

Minimizing thickness of deadfronted display assemblies

A system and method for verifying integrity of data signals communicated from a data transmit device to a receive device over a communications channel of limited bandwidth. The method comprising steps of: a) detecting instances of idle data transmit activity at the transmit device; b) accumulating data integrity information for data transmitted over the communication channel between detected idle transmit instances, the accumulating being performed by data integrity verifier devices at both transmit and receive devices; c) communicating accumulated data integrity information for data transmitted since a last detected idle data transmit instance during a current detected idle data transmit instance; and, d) verifying accumulated data integrity information communicated over the channel at the receiver device. The system and method of the invention may be used to provide intermediate data integrity checks when communication of packets belonging to a stream is interrupted without compromising bandwidth utilization. Moreover, the system and method of the invention may be used to provide data integrity verification for data communicated over two or more communications channels between instances of detected idle transmit states.

System and method for utilizing spare bandwidth to provide data integrity over a bus

A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

Data length control of access to a data bus

A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

Limiting write data fracturing in PCI bus systems

Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Method and system for multiple read/write transactions across a bridge system

Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent. In a similar manner, in delayed write operations, the write data may also be gathered from several write operations and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device.

Method and system for gathering and buffering sequential data for a transaction comprising multiple data access requests

Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

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Tucson, AZ, United States of America

Robert Earl Medlin