International Business Machines Corporation

Robert Earl Kruse

Sanjay Raghunath Deshpande

Robert Allen Drehmel

Philip E Milling

A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.

Method, apparatus, and computer program product for controlling data transfer

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In addition, a bus arbiter in the node controller parks a data bus towards a memory subsystem. The node controller does not use data buffer reservations. The data bus grant line to the memory controller is overloaded to use it as a back-pressure, get-off-the-bus signal as well as a normal data bus grant line. The fairness of the bus is thereby increased by creating a mechanism for getting a &ldquo;parked&rdquo; device off the data bus without the use of another dedicated signal between physical components. To ensure that the node controller may stream data to the memory subsystem, the bus is not reparked towards the memory subsystem until a configurable number of cycles after the data bus has been granted to the node controller.

Method and apparatus for increased performance of a parked data bus in the non-parked direction

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In order to reduce the delays in giving address bus grants, a bus arbiter for a bus connected to a processor and a particular port of the node controller parks the address bus towards the processor. A history of address bus grants is kept to determine whether any of the previous address bus grants could be used to satisfy an address bus request associated with a data bus request. If one of them qualifies, the data bus grant is given immediately, speeding up the data bus grant process by anywhere from one to many cycles depending on the requests for the address bus from the higher priority node controller.

Method and apparatus for avoiding data bus grant starvation in a non-fair, prioritized arbiter for a split bus system with independent address and data bus grants

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by introducing delays into the snoops of commands selected from its queues in certain circumstances. If the system is lightly loaded, the introduced delay is configured to be the minimum amount necessary to eliminate failed snoops with particular known bus timing conflicts. If the system is more heavily loaded, no delays are experienced in the selection of commands for snoop.

Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by node controllers. A node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, a node controller helps to maintain cache coherency. The node controllers must give simultaneous address bus grants to the address switch to initiate a snoop. Livelocks are detected individually by each node controller in an uncoordinated manner from a lack of successful snoops from the address switch to the node controllers. To break the livelock, address bus grants to the address switch are manipulated by the node controllers in a distributed, uncoordinated manner until a snoop is seen by the node controllers, thereby obviating the need for dedicated sideband signals on the bus.

Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by pacing commands selected from its queues in certain circumstances. After a command is selected for snoop from a particular queue, the node controller does not select another command for snoop from that particular queue until the command returns for snoop, at which time the node controller may introduce a configurable delay before allowing a command to be selected from that particular queues.

Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system

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Robert Earl Kruse