Disk Emulation Systems, Inc.

Database Excelleration Systems, Inc.

Solid Data Systems, Inc.

Robert E Warne

George B Tuma

Wade Bert Tuma

Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Disk storage subsystem with internal parallel data path and non-volatile memory

Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit. The error correction process corrects single bit hard errors in a stored digital data word of &ldquo;n&rdquo; bits according to the following steps. The process generates a parity bit for the n-bit word according to a predetermined algorithm prior to storing the word. The process then stores the digital data word in a selected storage location and also stores the parity bit. The process retrieves the stored n-bit word from the selected storage location. The process also retrieves the stored parity bit for the n-bit word. Then, the process generates a new parity bit for the retrieved word according to the predetermined algorithm. The new parity bit is compared with the retrieved parity bit. The process corrects the n-bit retrieved word only when the parity bits are different, by inverting the retrieved word and writing the inverted word to the selected storage location. The process retrieves the inverted word from the selected storage location and inverts the inverted word retrieved from the selected storage location.

Method for correcting single bit hard errors

Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the disk emulator includes a volatile storage medium, a parallel path, a nonvolatile media and a control circuit. The control circuit can store parallel data received on the parallel path into the nonvolatile media and supply parallel data from the nonvolatile storage media on the parallel path. Moreover, in a first mode of operation the control circuit can store data received from a disk controller at a location in the volatile storage medium and in a second mode of operation, the control circuit can retrieve data from the volatile storage medium and provide the retrieved data to the disk controller.

A disk storage subsystem for interfacing with a parallel path, a

Disk emulation system

Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central procssor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access ttime. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

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Markleeville, CA, United States of America

Robert E Warne