International Business Machines Corporation

Globalfoundries Inc.

Robert E Walkup

Alan G Gara

David L Satterfield

Philip Heidelberger

Michael K Gschwind

Valentina Salapura

Dong Chen

Paul William Coteus

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert William Wisniewski

Thomas M Gooding

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

George L Chiu

Todd Alan Inglett

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Peter Boyle

Ralph E Bellofatto

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

Kattamuri Ekanadham

Gary S Selwyn

Hao Yu

I-Hsin Chung

James C Sexton

Gyan Vatsaraja Bhanot

Hui-Fang Wen

David Joseph Klepacki

Simone Sbaraglia

Eoin M Lawless

Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

Opcode counting for performance measurement

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A method for application performance data collection includes steps or acts of: customizing a performance tool for collecting application performance data of an application; modifying the application by inserting the performance tool while the application does not need to be rebuilt from the source; executing the application; and collecting the application execution performance data such that only interesting data is collected. Customizing the performance tool proceeds by implementing at least one configurable tracing function that can be programmed by the user; compiling the function(s) into an object file; and inserting the object file into the performance tool using binary instrumentation.

Binary programmable method for application performance data collection

A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=&#x3a3;C(i,j)H(i,j)&#x2212; where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.

Optimizing layout of an application on a massively parallel supercomputer

An interferometer (18 or 40) is used to identify trace constituents in a plasma during processing semiconductor devices such as transistors. Light emissions collected from the processing chamber (10) are collimated by lens (14) and transmitted to the interferometer (18 or 40) which selectively allows therethrough particular wavelengths of light which are characteristic of the excitation emissions of certain atoms such as sodium and copper. The light intensity at the selected wavelengths is sensed by a photomultiplier tube (30). In one embodiment, the interferometer (18) is a Fabry-Perot type interferometer and the separation of the plates (20 and 22) which form the Fabry-Perot etalon is controlled using a piezoelectric driver (26). A signal processor (34) correlates the sensed light emissions from the photomultiplier tube (30) with the selected wavelength that is determined by the piezoelectric driver (26). In another embodiment, the interferometer (40) is a narrow bandpass interferometric filter which is tiltable with respect to the collimated incident light from the processing chamber (10). Tilting a narrow bandpass interferometric filter (42) with respect to incident light changes the path length through the filter (42) and allows for the selective transmission of certain wavelengths of light. By rapidly tilting the narrow bandpass interferometric filter (42) at a rate between 5-300 Hz with respect to the incident light, a narrow range of wavelengths on the order of 3 nm can be scanned.

Plasma constituent analysis by interferometric techniques

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Yorktown Heights, NY, United States of America

Robert E Walkup