International Business Machines Corporation

Robert E Vogelsberg

Stephen Dale Hanna

Gerald Donald Boldt

Kent S Norgren

Chaining or cascading two or more DMA devices to perform DMA transfers across common buses. DMA devices are modified to act as a bus slave relative to another DMA bus master device so that information can be transferred from one bus to another across a third bus common to the DMA devices. The slave DMA can cause the master DMA to stop sending data to limit the bandwidth requirements of the common bus.

Chained DMA devices for crossing common buses

Memory testing is performed by a dedicated hardware system, initialized by a system processor and employing the processor's DMA capability to allow the system to execute other programs without having to wait until memory testing is completed. The same hardware can be utilized as a memory scrubber.

Fast memory power-on diagnostics using DMA

Resource master and slave combinations operating from separate local clocks asynchronously even though there may be wide speed variations among the devices, eliminating the need to synchronize the trailing edges of generated control signals with the local clock so as to free access to the resource as soon as possible without introducing timing or logic hazards.

Fast asynchronous resource master-slave combination

Independent asynchronous bus master devices share a common bus with control lines serially connecting each bus master in a daisy-chain contiguration. A Bus Acknowledge signal is received by a local bus master which is thereby enabled to seize control of the bus without an input synchronization delay by first inhibiting synchronization means to prevent the passage of the Bus Acknowledge signal to a downstream device for a period of time sufficient to stabilize an output signal indicating such passage. In that manner, the output signal may be used to control the immediate enabling of local bus seizure thereby avoiding local synchronization delay.

Access control to a shared resource in an asynchronous system

A peripheral processing controller controls access to a peripheral memory by specialized peripheral devices. The specialized peripheral devices process all of the data independently of a central processor that simply supervises the system. The controller uses Memory Address Registers (MARs) to control the access to the memory by the peripheral devices. Each peripheral device selects a MAR, and each MAR includes a mode register. The start address and mode are set in each MAR by the supervising central processor. Also, each peripheral device is set by the processor to select a MAR. When the controller grants each peripheral device access to the peripheral memory, the peripheral device uses whatever mode and starting address has been initialized for the MAR selected by the device. Each time the device accesses the memory, the address in the MAR is incremented so the MAR is ready for the next access. In this way, a peripheral device will advance through a block of memory space. The mode is used to specify the end-of-block (EOB) condition for the block of memory space that the peripheral device is working with. The EOB may be based on the number of accesses by a device to the memory or it may be based on particular memory addresses.

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Boulder, CO, United States of America

Robert E Vogelsberg