Fujitsu Corporation

Lsi Corporation

International Business Machines Corporation

Robert E Stubbs

Mohamad H El-Batal

John R Kloeppner

David Larson

Gene Edstrom

Dennis E Gates

Jason M Stuhlsatz

Russell J Henry

Charles E Nichols

Jeremy D Stover

Macen Shinsato

Edde Tang Tin Shek

Dana J Burgess

Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack if the enclosure is mounted near the top of the rack.

Apparatus and systems having storage devices in a side accessible drive sled

A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.

Configurable storage array controller

Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Apparatus and methods for clustering multiple independent PCI express hierarchies

An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and a single set of interrupt status-registers. The interrupts are generated by the interrupt generator in an order determined by the order of tasks sent by the CPU to the interrupt generator and indicate completion of those tasks. The CPU can maintain in the storage element an ordered list of at least a contiguous subset of the tasks sent to the interrupt generator. The CPU can also maintain in the storage element a count of tasks sent to the interrupt generator as part of the contiguous subset. For each interrupt it generates the interrupt generator increments the count in the interrupt counter and writes the address of the interrupt to the interrupt status register. Because a single interrupt status register is used, only the status information for the latest interrupt is available in the register. When it has time to respond to an interrupt the CPU reads then resets the interrupt counter and reads the interrupt status register to determine the current interrupt count and interrupt address. From the current interrupt count and address and the contents of the ordered list and the task count the CPU is able to determine with certainty how many tasks previously sent to the interrupt generator are pending and accordingly generate new tasks to keep the interrupt generator busy.

Interrupt mechanism on NorthBay

A determination is made as to whether or not storage devices of a storage array are positioned in their proper physical locations in the array. To make the determination, a device identifier for each of the storage devices is utilized, together with a generated logical identifier. In a preferred embodiment, the device identifier is the serial number for the storage device and the logical identifier includes a combination of all the device identifiers for a particular logical volume of the storage array. Preferably, the logical identifier also includes system status information for use in enhancing fault tolerance. The logical identifier is written or updated upon the occurrence of predetermined events or conditions. Using the device identifiers and the logical identifier, an indication can be provided whenever the proper storage devices are not found in the logical volume whereby corrective action can be taken to avoid improper distribution to or reassembly of data from the logical volume.

Checking for proper locations of storage devices in a storage device

Checking for proper locations of storage device in a storage device array

A bus for transferring data is disclosed wherein the bus supports asynchronous, synchronous and high speed synchronous data transfers of varying size. The bus includes a master component for controlling data transfers with one or more slave components attached to the bus. Each data transfer is either received or supplied by the master via a set of data lines common to each slave component. Further, there are different control lines between the master and the slave components depending on the protocol(s) supported by each of the slaves. In particular, a slave supporting a high speed synchronous protocol is connected to the master by four control lines dedicated to providing control signals for implementing a high speed synchronous protocol handshake. Further, a fifth such control line is used to select a slave for a high speed synchronous data transfer when there is a plurality of high speed synchronous slaves.

Bus supporting a plurality of data transfer sizes and protocols

Checking for proper locations of storage devices in a storage array

Growing community of inventors

Longmont, CO, United States of America

Robert E Stubbs