Digital Equipment Corporation

Other

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Robert E Stewart

James B Keller

Stephen R Jenkins

David P Rodgers

John V Levy

Richard J Casabona

Thomas A Northrup

Simon C Steely, Jr

Stephen R Van Doren

Raj K Ramanujan

Barry J Flahive

William A Samaras

John DeRosa

Timothy Edwin Leonard

Sherry Tsi-chuan Lee

David Potter

Donald F Hooper

David N Cutler

William D Strecker

Paul J Natusch

Allan R Kent

Judson S Leonard

Barry A Henry

Milton V Mills

Ronald C Carn

Donald R Metz

Harold A Read

Charles E Kaczor

Alan Kotok

Eugene L Yu

Daniel L Murphy

Thomas R Ermolovich

John E Buzynski

Robert Giggi

Samuel Fuller

An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

High speed bus system that incorporates uni-directional point-to-point buses

A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

In accordance with the present invention, a method and apparatus is provided for maintaining the coherency of victim data from a time when the data is stored in a victim data buffer until a time when the data is written into a main memory. Alternatively, the coherency of the victim data is preserved until a determination is made that pending probe messages do not target the victim data. At that time the victim data buffer can be deallocated. With both arrangements, a central processing unit can release a victim data buffer at a point in time other than when the data that is stored therein is read from the buffer. Thus, the central processor unit can perform the release or deallocation of the buffer when it is most efficient and when no further access to the data is required.

Separate victim buffer read and release control

In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim data, using a set of victim data buffers coupled to a central processing unit of a computer system. Storage locations referred to as a 'victim valid bit' and a 'probe valid bit' are associated with each victim data buffer in the computer system to indicate a release condition for the coupled victim data buffer. With such an arrangement, the victim data buffer can be deallocated when the victim valid bit and the probe valid bit have both been cleared.

Independent victim data buffer and probe buffer release control utilzing

A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables. Since consecutive pages of the page table in virtual memory reside in consecutive page frames in physical memory, a virtual address in the page tables can be translated to a physical address by adding the page frame number from the prototype page table entry to the virtual page number in the virtual address. The prototype page table entry contains a page-frame number that is equal to the page-frame number of the first page of the page table minus the virtual-page number of the first page of the page table.

Method for addressing page tables in virtual memory

Combined pet comb and flea electrocuter

Virtual address to physical address translation using page tables in

In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.

Apparatus and method for providing a settling time cycle for a system

In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

Apparatus and method for responding to an aborted signal exchange

A computer interconnect coupler has a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment code responsive to the imcoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added and a hierarchical rotating priority scheme enables the additional channels to have equal priority with the previously existing channels without requiring reprogramming. Moreover, the processing and queueing of routing requests is made more effective by grouping the requests into different priority levels and using separate but duplicate arbitration logic to resolve simultaneous requests within the same priority group.

Computer interconnect coupler employing crossbar switching

A microprogrammed data processing system uses a plurality of control stores to control the data processing system in response to a macroinstruction sequence. Between each control store is a latch element resulting in a given address being applied to each control store at different system clock cycles. The corresponding microinstruction segment from each control store is therefore provided at different clock cycles, making it possible to coordinate the microinstruction segment with the corresponding flow of data through the central processing unit. The use of a plurality of control stores can reduce the number of gate elements needed to delay microinstruction segments.

Microprogrammed data processing system using latch circuits to access

Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other, the source and destination buffer names are contained right in the transmitted packet. The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be executed with the commands locally generated at the second node, without need for host interruption.

Apparatus for transferring blocks of information from one node to a

A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.

Apparatus and method for providing a cache memory unit with a write

Apparatus for decoding a self-clocking, encoded signal wherein a series of data bits is encoded such that for each data bit, the encoded signal contains a first transition, and, for each data bit for which the succeeding data bit has the same binary value, the encoded signal contains a second transition occurring within a predetermined time interval after the first transition. The decoding apparatus comprises storage means responsive to a clocking signal of at least a predetermined minimum pulse width, received at a clock input for storing a sample of a digital signal received at a data input, the storage means having at least one output indicative of the stored value; an exclusive-OR gate; a first signal path from the output of the storage means through the exclusive-OR gate to the clock input of the storage means; a second signal path from the source of the encoded signal through the exclusive-OR gate to the clock input of the storage means; and a third signal path from the source of the encoded signal to the data input of the storage means; the time for a signal to propagate along the first signal path being at least as long as the minimum pulse width required to clock the storage means; and the difference between the time for a signal to propagate along the second signal path and the time for a signal to propagate along the third signal path being at least as long as said predetermined time interval.

Decoder for self-clocking serial data communications

An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

Interface for serial data communications link

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Stow, MA, United States of America

Robert E Stewart