Motorola Corporation

Motorola Solutions, Inc.

Motorola Mobility LLC

Symbol Technologies, LLC

Robert E Stengel

Nicholas Giovanni Cafaro

David E Bockelman

Scott A Olson

Thomas L Gradishar

David L Muri

Bruce M Thompson

Joseph P Heck

Andrew Tomerlin

Paul H Gailus

Charles R Ruelke

Frederick L Martin

James S Irwin

Spyros Kyperountas

Wang-Chang A Gu

Sumit Anil Talwalkar

Robert S Kaltenecker

Joseph A Charaska

Ralph T Enderby

Geetha B Nagaraj

Jui-Kuo Juan

William Paul Alberth, Jr

Paul D Marko

Armin Werner Klomsdorf

Antonio Faraone

Gustavo Dario Leizerovich

Lawrence Marvin Ecklund

Qicai Shi

Quirino Balzano

Branko L Avanic

Ke Keryn Lian

Roger A Davenport

Robert J O'Dea

Lawrence F Cygan

Neiyer S Correal

Vernon Anthony Allen

Lei Zhao

Robert J Higgins

Lijun Bai

Francis R Yester, Jr

Enrique Ferrer

Kenneth David Cornett

Matthew R Perkins

Douglas H Weisman

Stephen B Einbinder

Manuel P Gabato

Robert G Kinsman

Daniel E Brueske

Jeffrey B Wilhite

Ronald E Sharp

Arthur G Burns

Carlo Di Nallo

Edwin E Bautista

Leonard F Altman

Robert L Benenati

George W Marlin

Ronald C Alford

Ralf Hekmann

Joshua E Dorevitch

Charles A Backof

Frederick J Martin

Charles W Nejdl

Nicholas G Cafaro

Jeffrey B White

Manuel Gabato, Jr

Wen Yu

Scott Miller

Stephen T Machan

Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals&#x2014;that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals&#x2014;to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

Systems and methods for generating injection-locked, frequency-multiplied output signals

A Radio Frequency Identification (RFID) reader is provided that receives a digital input signal, converts the digital input signal to an analog input signal, and determines whether the digital input signal is an unmodulated signal or is modulated with information. When the digital input signal is modulated with information, the RFID reader filters the analog input signal to produce a filtered analog input signal and transmits the filtered signal. When the digital input signal is an unmodulated signal, the RFID reader bypasses the filtering of the analog input signal to produce an unfiltered analog input signal and transmits the unfiltered analog input signal.

Method and apparatus for transmitting a signal by a radio frequency identification reader

A communication device includes a receiver that is capable of canceling in -channel interference. The receiver includes an antenna for receiving a wireless signal comprising in-channel components and an out-of-channel component, wherein the in-channel components comprise a desired component and an in-channel interference component. A first filter of the receiver filters the wireless signal by blocking at least a portion of the out-of-channel component to produce a first signal comprising the in -channel components, and at least a second filter of the receiver filters the wireless signal by blocking at least a portion of the in-channel components to produce a second signal comprising the out-of-channel component. An in-channel interference estimator of the receiver generates an in-channel interference estimation signal based on the second signal. And a combiner of the filter combines the first signal and the second signal to at least partially cancel the in-channel interference component of the first signal.

Method and apparatus for in-channel interference cancellation

A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Method and apparatus for single port modulation using a fractional-N modulator

A multi-antenna device () comprising a set of antennas (-), a set of receivers (-), a multiplexer (), a baseband filter (), an analog-to-digital converter (), and a de-multiplexer (). The receivers (-) can be linked to the antennas (-) in a one-to-one manner. The multiplexer () can generate a composite analog signal from a set of different analog signals, one received from different ones of the antennas (-). The baseband filter () can filter the composite analog signal. The analog-to-digital converter () can convert the composite analog signal after being filtered by the baseband filter into a composite digital signal. The de-multiplexer () can generate a set of different digital signals from the composite digital signal. Each of the different digital signals can correspond to one of the different analog signals in a one-to-one manner.

Method and apparatus for a multi-antenna device that uses a single baseband filter and analog-to-digital converter

A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.

Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer

A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Method and system for managing digital to time conversion

A radio communications deviceincluding a processorhaving a digital signal processor (DSP) coupled to a transceiverThe transceiver includes a digital-to-phase synthesizer having one or more independently variable frequency or phase signal outputs coupled to a transmitter and/or to a receiver. The variable frequency and phase outputs of the digital-to phase synthesizer are mixed with corresponding received signals and are capable of frequency or phase modulating information signals for transmission. Amplitude modulated signals may be provided through polar modulation by combining synthesizer outputs at a summer.

Radio transceiver architectures and methods

A frequency generation unit is provided that permits a receiver to tune from channel to channel without cycle skipping and in which compensation for phase offset introduced during tuning is provided. The frequency generation unit includes a fractional-N synthesizer, a voltage controlled oscillator (VCO), and a direct digital synthesizer (DDS). The fractional-N synthesizer generates frequencies from the VCO as well as a temperature controlled crystal oscillator. Outputs from the fractional-N synthesizer are supplied both the VCO and the DDS to control the VCO and DDS. The combination of the voltage controlled oscillator and fractional-N synthesizer is perpetually locked. The fractional-N synthesizer is maintained in a locked condition. The VCO output is provided to the DDS. An output from the DDS or from the fractional-N synthesizer forms the output signal of the frequency generation unit.

Device and method for phase compensation

A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The method further includes coding the periodic square wave LO signal of the first phase and the periodic square wave LO signal of the second phase synchronously with the chopping signal to generate a first set of synchronized signals () and a second set of synchronized signals (), respectively. A phase difference between the first phase and the second phase is a predefined value. The RF signal is processed with the first set of synchronized signals () and the second set of synchronized signals () to obtain an in-phase intermediate frequency (IF) signal () and a quadrature-phase IF signal (), respectively.

Method and apparatus for processing radio frequency signals

A method and frequency converter for a radio rapid frequency signal scanning and including a local oscillator signal synthesis source () producing a local oscillator signal () with local oscillator bursts (). The local oscillator bursts () contain pulse width modulated RF frequency pulses (). Each local oscillator burst having, for a pre-determined duration, RF frequency pulses within an effective amplitude above a pre-determined threshold (). Each local oscillator burst () having also has effective amplitude pulse shaping envelope () that reduces at least one frequency domain component magnitude () of the local oscillator signal (). A radio frequency mixer () receives an RF signal input () and the local oscillator signal to produce an output signal () at a frequency related to a combination of a frequency of the RF signal input and a frequency of the local oscillator signal.

Spectrally constrained local oscillator switching

A frequency generator () takes a signal source (clock or carrier) () and generates a edge encoded direct digital modulated differential output signal (). The differential signal () is applied to a frequency extension quadrature generator (FEQG) (). The FEQG () includes a fractional differential wavelength delay locked loop (DLL) () and a frequency multiplier (). The DLL () generates a control voltage () with which to control delays of the edge encoded modulation signal (). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (), to provide the output signal set

Method and apparatus for reconfigurable frequency generation

A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.

Clock data recovery systems and methods for direct digital synthesizers

A DPC () includes: a frequency source () for generating a clock signal; a delay line () for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device () for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices () and a combining network. A method for use in a DPC includes: receiving () a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting () at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating () an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Method and apparatus for a digital-to-phase converter

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Direct digital synthesizer with variable reference for improved spurious performance

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Pompano Beach, FL, United States of America

Robert E Stengel