Xilinx, Inc.

Monterey Design Systems, Inc.

Robert E Shortt

Salil Ravindra Raje

James S Koford

Lawrence Thomas Pileggi

Douglas B Boyle

Majid Sarrafzadeh

David A Knol

Sharad Malik

Shay Ping Seng

Christopher J Dunn

Gary K Yeap

Feroze P Taraporevala

Abhijeet Chakraborty

David Gluss

Krishnan Subramanian

Lilly Shieh

Dennis Yamamoto

Tong Gao

Emre Tuncer

Dinesh D Gaitonde

Joseph T Rahmeh

Eric McCaughrin

Sam Jung Kim

Archie Li

Yau-Tsun Steven Li

Satamurthy Pullela

A method of circuit design includes receiving a user input selecting a first interface of a circuit block of a circuit design as a source interface in creating a connection within the circuit design and selecting a second interface of the circuit design as a candidate destination interface for the connection using a processor. The method further includes determining compatibility between the second interface and the first interface and indicating compatibility of the second interface with the first interface for the connection.

Electronic design automation tool for guided connection assistance

A method is provided for generating an implementation of an electronic design. Information describing a set of strategies is specified. Each strategy of the set includes one or more options for directing the generation of an implementation of the electronic design, with each option being a set of one or more input parameter values to an implementation tool. The set of strategies is displayed and a subset of the set of strategies is selected in response to user input. For each strategy of the subset, a respective implementation of the electronic design is generated from a specification of the electronic design in a hardware description language. The option or options of each strategy are input to one or more implementation tools to direct the generation of the respective implementation for the strategy. For each strategy of the subset, quality metrics are displayed for the respective implementation of the electronic design.

Strategies for generating an implementation of an electronic design

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

Growing community of inventors

Sunnyvale, CA, United States of America

Robert E Shortt