Square D Company

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Sandia Corporation

National Technology & Engineering Solutions of Sandia, LLC

Robert E Riley

Cameron H Musgrove

James C West

Bobby G Rush

Various technologies for mitigating distortion in coherent image products generated from SAR data are described herein. Synthetic aperture radar (SAR) datasets generated based upon SAR returns from first and second passes of a SAR platform over a scene are received. The SAR datasets can be co-notched at matching sample indices to improve coherence of SAR images generated from the datasets. Windowed SAR data is generated by applying independent windows to subsets of each of the datasets to reduce sidelobe levels of their image impulse responses. Coherent image products are generated based upon the windowed SAR data, wherein an image quality of the coherent image products is improved as compared to coherent image products generated based upon the SAR datasets.

Co-notch and independent windowing to mitigate interference in SAR-based imagery

Pre-processing is applied to a raw VideoSAR (or similar near-video rate) product to transform the image frame sequence into a product that resembles more closely the type of product for which conventional video codecs are designed, while sufficiently maintaining utility and visual quality of the product delivered by the codec.

Pre-processing SAR image stream to facilitate compression for transport on bandwidth-limited-link

A programmable data link module is used on a time division multiplex data bus. The module is functional as an input device, an output device, or both as an input and output device. It can receive data from the data bus during the selected time slot for a selected number of frames to control output devices connected to it. The data link module includes an input circuit for generating a data output signal data to the data bus in response to the input signals from an input device coupled to the module. The input circuit includes a programmable input communication mode selector, allowing the data bus and the data link module to function with or without a host computer. The mode selector provides simplex or duplex.

I/O module for a serial multiplex data system with a programmable

A programmable data link module is used on a time division multiplex data bus. The module is functional as an input device, an output device, or both as an input or output device. It can receive data from the data bus during a selected time slot for selected number of frames to control output devices connected to it. The data link module includes an input circuit for generating a data output signal data to the data bus in response to input signals from in input device coupled to the module. The input circuit includes a programmable input communication mode selector, allowing the data bus and the data link module to function with or without a host computer. The mode selector provides simplex or duplex.

I/O Module for a serial multiplex data system with a programmable

A programmable data link module is used on a time division multiplex data bus. The module receives data from the data bus during a selected time slot for a selected number of frames. The data link module includes an input circuit for generating a data output signal data to the data bus in response to input signals from an input device coupled to the module. The input circuit includes a programmable input voltage level selector, allowing different voltage rated input devices to be used with the data link module. A hysteresis circuit sets a minimum voltage level threshold representative of the input device being in one logic state and a maximum voltage level threshold representative of the input device being in another logic state.

I/O module for a serial multiplex data system with a programmable input

A programmable data link module for use with a time division multiplex data bus includes an input and a high voltage protection circuit to prevent outputting of data to the data bus under several different operation conditions. These include programming of the data link module and verification of the programming. The data link module also inhibits the outputting of data signals to the data bus in response to changes of the input signals from a local input device until the power to the data link module has stabilized for a preselected period of time. The high voltage protection circuit protects the data link module from excessive overvoltage from other devices connected to the data bus.

Module for a serial multiplex data input protection circuit

A programmable data link module is used on a time division multiplex data bus. The module receives data from the data bus during a selected time slot for a selected number of frames. The data link module includes an input circuit for generating a data output signal data to the data bus in response to input signals from an input device coupled to the module. The input circuit includes a data bus integrity checker for determining whether the data bus is intact. A test signal is sent by a master clock source to the data link module and if it is properly received, the integrity checker will permit the data link module to received data signals from the data bus.

I/O module for a serial multiple data system with a data bus integrity

A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection circuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programming circuit (232) for accepting programming over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

Data link module for time division multiplexing control systems

A programmable data link module is used on a time division multiplex data bus and includes a system master clock signal. The module is functional as an input device, an output device, or both as an input and output device. It receives data from the data bus during a selected time slot for a selected number of frames to control output devices connected to it. The data link module includes a clock loss signal for generating an inhibit signal when a loss of the master clock signal is detected. The inhibit signal will prevent any changes to the state of the output device during the duration of the loss of the master clock signal.

A programmable data link module is used on a time division multiplex data bus having a repetitive time frame, each time frame having a plurality of time slots. The module receives data from the data bus during a selected time slot for a selected number of frames. The data link module includes a data verifier for storing the received data during the selected frames and inhibits outputting of data signals to the data bus until a repetitive occurrence of the received data over the selected number of frames has been verified.

Module with data verification for a serial multiplex data system

A programmable data link module for use with a time division multiplex data bus includes a word extender module. The module can receive, send, or receive and send data over the data bus during a preselectable time period. The time period is defined by a programmable starting address and an ending address. The data can be single or multibit and variable length as determined by the time period selected.

Data module with variable data word length for a serial multiplex data

A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection circuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programing circuit (232) for accepting programing over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection circuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programing circuit (232) for accepting programming over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

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Jackson, MS, United States of America

Robert E Riley