Gte Automatic Electric Incorporated

Gte Communication Systems Corporation

Ag Communication Systems Corporation

Other

Robert E Renner

Thomas J Perry

Greig R Detering

John Wesley Spenik

John S Young

Han Kem

David A Kutz

Kuang-Cheng Hu

Kevin W Williams

A method of bit rate adaption between a user data rate and an adapter data rate using the ECMA 102 protocol. The user data is received from a user terminal at a user data rate, the rate adapted data is transmitted at an adapted data rate, and the adapted data rate is greater than the user data rate. The user data is either in a asynchronous or a synchronous format and contains a start element and at least one stop element. The method involves the steps of: (1) converting the user data into an intermediate data; (2) storing the intermediate data in a receive buffer; (3) only if the user data is in an asynchronous data format, adding stop elements to the intermediate data; (4) transferring the intermediate data in the receive buffer to an intermediate buffer; (5) constructing a frame using data from the intermediate buffer; (6) storing the frame in a transmit buffer, and; (7) transmitting the frame where the step of transmitting changes the frame into the rate adapted data.

Method of bit rate adaption using the ECMA 102 protocol

A method of bit rate de-adaption between an adapted data rate and a user data rate using the ECMA 102 protocol. The user data is transmitted from a data adapter to a user terminal at a first data rate, the adapted data is received by the data adapter at a second data rate, and the second data rate is greater than the first data rate. The adapted data contains a start element and a plurality of data elements while the user data contains a start element and at least one stop element. The method involves the steps of: (1) Receiving the adapted data at the second data rate; (2) Converting the adapted data into a frame; (3) Storing the frame in a receiver buffer; (4) Dissecting the frame into an intermediate data; (5) extracting the plurality of data elements from the intermediate data; (6) Storing the plurality of data elements in a transmit buffer; (7) Converting the first plurality of data elements to the user data by adding the second start element and the at least one stop element; and (8) Transmitting the user data to the user terminal at the first data rate.

Method of bit rate de-adaption using the ECMA 102 protocol

A data adapter for simultaneously providing a low speed channel, a first high speed data channel, and a second high speed channel over a two wire connection; the two wire connection connects the data adapter to a telephone system. The data adapter includes a line transceiver connected to the two-wire connection, the line interface provides a full duplex transmission link with the telephone system over the two-wire connection. A telephone interface converts data between the first high speed channel and a telephone instrument. A rate adapter converts data between the second high speed channel and a data processing equipment. A protocol controller performs a packet protocol on the low speed channel, and routes the first high speed channel to the telephone interface and the second high speed channel to the rate adapter. A processor that receives and transmits messages through the protocol controller over the low speed channel to the telephone system, and in response to information received over the low speed channel, alternatively information received from the rate adapter, the processor controls the data adapter.

Simultaneous voice and data system using the existing two-wire inter-face

In order to accomplish the object of the present invention there is provided a network independent clocking (NIC) circuit which allows a local synchronous master to exchange data with a local data adpater. The NIC circuit includes a phase measuring block for continually generating a local phase difference indicator, where the local phase difference indicator indicates a phase relation between the local data adapter and the local synchronous master. The local phase difference indicator is transmitted to a remote data adapter. Back locally, a phase difference indicator is received from a remote data adapter. A baud clock is generated and used to transfer data from the data adapter to the synchronous master, the baud clock generator uses the phase difference indicator to recreate the phase difference between the remote data adaper and the remote synchronous master.

Network independent clocking circuit which allows a synchronous master

This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.

Test point adapter for chip carrier sockets

A time shared multiport conference arrangement includes an additive PCM speaker circuit. The additive PCM speaker circuit eliminates the need for loudest speaker detection and the last speaker memory of conventional conferencing arrangements. The additive PCM speaker circuitry operates in an on-line, real time environment to allow rapid summing of speakers' PCM voice samples. Since the PCM voice samples are logarithmic in nature, they are not directly combinable. The additive PCM speaker circuitry provides a storage medium which is preprogrammed with resultant values. These resultant values each correspond to a PCM addition of the values of two input speaker's PCM voice samples. The additive PCM speaker circuit simplifies the complex processing logic usually associated with loudest speaker detection systems and thereby improves the real time operation of the conferencing arrangement.

Additive PCM speaker circuit for a time shared conference arrangement

A method for generating additive combinations of PCM voice samples separates the samples into magnitude portions and sign portions. The magnitude portion of each PCM voice sample is converted from compressed PCM form to linear form. The magnitudes of the two voice samples, in linear form, along with their respective signs are added together to form a resultant linear value. If there is any overflow as a result of the addition, the resultant value is truncated so as not to exceed a maximum allowable value. The resultant value is then converted from linear form to compressed PCM form along with the proper sign. These steps are iterated for each possible value of the input PCM voice samples. These resultant values are stored in a storage medium for rapid on-line use by a switching system. Off-line generation of combined PCM samples saves system real time as compared to generating these combinations on-line in real time.

Method for generating additive combinations of PCM voice samples

This circuit facilitates the synchronization of two copies of digital control units. These digital control units control a number of digital spans. One copy of this circuit is active at any one particular time. This one copy drives all the remaining circuitry of the digital span interface for both copies of the digital control unit. The other copy of this circuit is typically in the ready-standby mode. It is not actively driving the remainder of the circuitry within its own copy. When one copy of the digital control unit is brought on-line, a framing operation must be performed to determine the proper framing bit for both copies. Circuitry in the cross-copy data path monitors an attempt to synchronize the two digital control unit copies. The data which is sent cross-copy is modified so that all data bits are at logic 1, except for a bit which the active copy believes is the proper S-bit or framing bit. In this manner, the standby copy cannot reframe on any bit, except the one which the active copy believes is the proper framing and synchronization bit.

Synchronization circuitry for duplex digital span equipment

Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. Synchronization circuitry includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors framing alarm signals from its own copy as well as from the other copy of the digital span control unit. This circuitry detects whether the framing alarm signals for each copy are identically synchronized. If these framing alarm signals are not identically synchronized, then one copy of the circuitry executes a hold (wait) operation for the other copy of the circuit to perform its reframing operation. For non-error conditions, the wait places the two copies back in synchronization. This arrangement applies stringent checking criteria to framing and synchronization bits, which have been previously found, to insure that these bits are the correct ones. As a result, the duplex units are more likely to remain synchronized.

Frame checking arrangement for duplex time multiplexed reframing

Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. The present synchronization arrangement is an additional duplex control circuit. This synchronization arrangement includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors data ready signals from its own copy as well as from the other copy of the digital span control unit. Other signals indicate whether the circuit is operating in a simplex or duplex mode and which circuit is the active and which is the standby copy. This circuitry detects whether the data ready signals for each copy are identically synchronized. If these data ready signals are not identically synchronized, then one copy of the circuitry waits a predetermined scan cycle time for the other copy of the circuit to catch up. For non-error conditions, the wait places the two copies back in synchronization. In order to avoid delaying down stream processing, this arrangement addresses these signals ahead of the time for which they are required for processing by the circuitry.

Synchronization arrangement for time multiplexed data scanning circuitry

The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.

Circuit for duplex synchronization of asynchronous signals

This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.

Duplex central processing unit synchronization circuit

Circuitry for validating the integrity of PCM data transmitted through a digital switching network is shown. The space stage of the switching system requires that appropriate data validity be maintained throughout. A parity scheme is employed to fulfill this requirement. For detection of invalid parity, an alarm notification is sent to the central processing unit (CPU) of the switching system. The CPU may then interrogate the space switching circuitry to determine the particular location of the parity failure. In addition, the circuitry provides for a testing feature, such that, the operation of the parity checking circuits may be validated.

Parity checking arrangement for a remote switching unit network

A time-space-time-space-time switching network is composed of a subscriber connected to a remote unit network having a time and space switching stage. The subscriber is then connected to a central office switching system having a time-space-time switching network. Alternatively, the switching network may comprise a subscriber locally connected through the time-space-time switching network of the central office switching system to the space and time stages of the remote switching unit. The remote unit network and the central office network are interconnected by a number of digital spans. In addition, the remote unit and the central office each provide for local to local traffic. That is, traffic which is transmitted only within its own switching network.

T-S-T-S-T Digital switching network

A remote switching unit which serves a large digital switching system is shown. The remote switching unit is CPU controlled and interconnects local subscribers to the large switching system. Digital spans connect the remote switching unit to the large switching system. A space switching stage provides for switching local traffic (traffic with the remote switching unit) and remote traffic (traffic from or to the large switching system). In addition, the remote switching unit provides an extended switching capacity with connections to smaller switching units.

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Glendale, AZ, United States of America

Robert E Renner