Infineon Technologies Ag

Advanced Micro Devices Corporation

Netapp, Inc.

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Globalfoundries Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Infineon Technologies LLC

Robert E Ober

Roger D Arnold

Erik K Norden

Daniel F Martin

Bret S Weber

Neil Stuart Hastie

Timothy E Hoglund

R Stephen Polzin

Robert W Warren, Jr

Sagheer Ahmad

William T Edwards

Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings.

Multi-mapped flash RAID

Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction.

Method and system for local caching of remote storage data

Disclosed is a coherent storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction. Other NIC's on other hosts may also cache network storage data. These NICs may respond to transactions from the first NIC by supplying data, or changing the state of data in their caches.

Method and system for maintaining data coherency across a network

An apparatus for keeping a VPN session alive on a portable computer system such as a laptop computer includes a processor that executes instructions that implement application software. The laptop computer system also includes a wireless module that may communicate with a wireless network such as a wireless wide area network including wireless telephone networks, for example. In addition, the wireless module may establish a virtual private network (VPN) connection with a computer network via the wireless network. The wireless module includes a processing unit that may execute instructions that cause information to be transmitted to a host portion of the virtual private network connection at one or more predetermined times.

Method and apparatus for keeping a virtual private network session active on a portable computer system including wireless functionality

A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.

Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation

An apparatus for logging and reporting network parameters within a portable communication device that includes a processor and a wireless module that may communicate with a wireless network such as a wireless telephone network, for example, via a wireless connection. The wireless module may determine characteristic information associated with the wireless connection and may provide the characteristic information to the processor. The processor may format the characteristic information for transmission and then transmit the formatted characteristic information to the wireless network. In addition, the processor may store the characteristic information within the portable communication device for future aggregation and transmission.

Apparatus and method for wireless network parameter logging and reporting within a portable device having wireless communication functionality

A portable computer system such as a laptop computer, for example, includes a first processor that may execute instructions corresponding to application software during a first mode of operation. The portable computer system also includes a second processor that may execute the instructions during a second mode of operation. The first processor and the second processor may be heterogeneous processors. Further, operation of the first processor and the second processor in the first mode and the second mode may be dependent upon which of a plurality of system preferences have been selected.

Portable computing platform having multiple operating modes and heterogeneous processors

A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

Program tracing in a multithreaded processor

Thread ID in a multithreaded processor

A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

Variable length instruction pipeline

An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.

Configurable real-time trace port for embedded processors

A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.

Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events

A power management system for a microcontroller. The power management system includes a power management state machine for controlling a power mode of a central processing unit (CPU) and each subsystem within the microcontroller. Each microcontroller subsystem is connected to the system through a configurable peripheral interface (FPI). Each FPI includes a software configuration register (SFR) that can be configured by an operating system or application program. The SFR for the various FPIs can be preconfigured to allow the response to each of the power modes of the power management state machine to be independently controlled for each subsystem.

Power management and control for a microcontroller

A processor comprises a central processing unit being clock driven and having a static design. A memory is coupled with the central processing unit for storing interrupt routines and data. An interrupt control unit is coupled with said central processing unit for generating interrupt signals. An interrupt execution unit is provided for executing interrupt routines. If no interrupt routine is being executed the central processing unit is stopped from operating.

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San Jose, CA, United States of America

Robert E Ober