Xerox Corporation

Permanent Images, Inc.

Robert E Markle

George E Mager

Lamar T Baker

George K Tu

James M Donohue

Stephen P Wilczek

George R Cogar

Permanent gray-scale reproductions including half-tone images. A refractory background region bears refractory thin-film dichroic filter means patterned to conform to the reproduced half-tone image. Preferred background region materials include metals, semiconductors, and ceramics; the thin-film materials are preferably oxides or nitrides of metals and semiconductors. If the refractory materials are appropriately selected, the reproductions are highly resistant to chemical and thermal deterioration and should have useful lives in the hundreds of thousands of years.

Permanent reproductions and formation method therefor

A copy reproduction machine is subdivided into discrete operating modules and coupled together by a shared communication line over which operating messages from and to the modules are transmitted. Each module includes a receiver for intercepting and capturing messages bearing the module's address and a transmitter for transmitting messages from the module and addressed to other modules over the shared communication line.

Message transmitting system for reproduction machines and copiers

A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.

Split programmable logic array

The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.

Chip topography for MOS integrated circuitry microprocessor chip

A circuit for storing data in a random access memory containing one defective bit per word. A separate read-only memory device or programmable logic array is provided to produce an interrupt bit whenever a memory location containing a defective bit is addressed, where a defective bit is defined as one that is stuck at 1 or stuck at 0. If an interrupt bit is generated the data word is read out from memory and compared to the original. If an equality exists, nothing further is required. If there is an inequality the data word is complemented and stored, and a flag bit is set. When data is read from memory, if the flag bit is set, the data word is complemented again before being used.

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Rancho Palos Verdes, CA, United States of America

Robert E Markle