Intel Corporation

Other

Robert E Larsen

Joseph H Salmon

Sanjay S Talreja

Peter K Hazen

Charles W Brown

Ranjeet Alexis

Kerry Dean Tedrow

Sandeep K Guliani

Jahanshir J Javanifard

Khandker N Quader

Terry L Kendall

Harry Q Pon

Robert N Hasbun

Mase J Taub

Albert Fazio

James Brennan, Jr

Chaitanya S Rajguru

David A Leak

Marcus E Landgraf

Collin Ong

Lance W Dover

Kurt B Robinson

Richard J Durante

Christopher John Haid

Vishram P Dalvi

Bharat M Pathak

Cesar Galindo

Edward M Babb

Steve R Eskildsen

Michael G Hahn

Terry D West

Jahanshir J Jayanifard

Wai Keung Tsang

Dhiraj Parmar

James Chan

Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset.

Non-volatile configuration data storage for a configurable memory

A low-power input buffer for a nonvolatile writeable memory is described. The low-power input buffer accepts input signals having one of a number of pairs of logic levels. The low-power input buffer provides output signals having a pair of logic levels that may differ from the logic levels of the input signal. The low-power input buffer comprises an inverter that receives an input signal, a circuit with a relatively low voltage drop, and a feedback pull-up device. The circuit with the relatively low voltage drop causes the low-power input buffer to accept input signals having one pair of logic levels while providing signals that may have a different pair of logic levels. The feedback pull-up device prevents the low-power input buffer from drawing leakage current. The low-power input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply output as the nonvolatile writeable memory. The low-power input buffer uses input signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Self-configuring input buffer on flash memories

A read-while-write memory device. The read-while-write memory device includes a read memory plane and a write memory plane. A first number of read sense amplifiers greater than one is coupled in parallel to the read memory plane in response to a memory read operation. A second number of verify sense amplifiers greater than zero and less than the first number is coupled to the write memory plane in response to one of a memory write or erase operation.

Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers

A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

Method and apparatus for preventing the fraudulent use of a cellular telephone

An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.

Method and apparatus for placing a memory in a read-while-write mode

An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

Apparatus and method using volatile lock and lock-down registers and for

A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Method and apparatus for fast production programming and low-voltage

A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.

Flash memory partitioning for read-while-write operation

A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Self-configuring interface architecture on flash memories

A high-speed output buffer for a nonvolatile writeable memory is described. The high-speed output buffer receives signals from the nonvolatile writeable memory having a pair of logic levels. The high-speed output buffer provides output signals having a pair of logic levels that may differ from the pair of logic levels of the signal received from the nonvolatile writeable memory. The high-speed output buffer comprises two inverters, a pull-up device, and a circuit with a relatively low voltage drop. The circuit with the relatively low voltage drop causes the high-speed output buffer to receive signals having one pair of logic levels while providing high-speed output signals having another pair of logic levels which may differ from the pair of logic levels of the received signal. The high-speed output buffer is coupled to a different power supply output from the nonvolatile writeable memory. The high-speed output buffer uses input and output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

1.8 volt output buffer on flash memories

A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Input/output power supply detection scheme for flash memory

A nonvolatile memory includes a memory array and a buffer circuit for applying data read from the memory array to external circuitry. A compensation circuit is coupled to the buffer circuit for providing output compensation to the buffer circuit when enabled. The buffer circuit has (1) a first output speed when the compensation circuit is enabled and (2) a second output speed when the compensation circuit is disabled. A configuration circuit is coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured between the first and second output speeds. A method of configuring a nonvolatile memory between a first output speed and a second output speed is also described.

Nonvolatile memory with output mode configuration

An integrated circuit arrangement for providing programming voltages to a flash EEPROM memory array including an arrangement for selecting subsets of bits of a word which is to be programmed and applying programming voltages only to the memory transistors of a selected subset.

Method and apparatus for sequential programming of the bits in a word of

An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

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Shingle Springs, CA, United States of America

Robert E Larsen