Freescale Semiconductor,inc.

Motorola Corporation

Adeia Semiconductor Bonding Technologies Inc.

Robert E Jones

Paul W Sanders

Michael F Petras

Peter Zurcher

Papu D Maniar

Bruce E White

Chandrasekaram Ramiah

Olubunmi O Adetutu

Gregory S Spencer

Bradley M Melnick

Syed M Alam

Ted R White

Scott K Pozder

Ajay Jain

Eric D Luckowski

Bo Jiang

Carole C Barron

Jill C Hildreth

Rickey S Brownson

Peir-Yung Chu

Sebastian Csutak

Terry Grant Sparks

Hisao Kawasaki

Kathleen C Yu

Douglas R Roberts

C Joseph Mogab

Reza Moazzami

David G Kolar

Andrew C Campbell

Lynne M Michaelson

Brad Smith

Ajay Somani

Cindy K Goldberg

Peir Chu

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Methods of forming 3-D circuits with integrated passive devices

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

3-D ICs () with integrated passive devices (IPDs) () having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates () coupled by through-substrate-vias (TSVs) (). An active device (AD) substrate () has contacts on its upper portion (). An isolator substrate () is bonded to the AD substrate () so that TSVs () in the isolator substrate () are coupled to the contacts () on the AD substrate (), and desirably has an interconnect zone () on its upper surface. An IPD substrate () is bonded to the isolator substrate () so that TSVs () therein are coupled to the interconnect zone () on the isolator substrate () and/or TSVs () therein. The IPDs () are formed on its upper surface and coupled by TSVs () in the IPD () and isolator () substrates to devices () in the AD substrate (). The isolator substrate () provides superior IPD () to AD () cross-talk attenuation while permitting each substrate () to have small high aspect ratio TSVs (), facilitating high circuit packing density and efficient manufacturing.

3-D circuits with integrated passive devices

A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.

Semiconductor device with photonics

A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.

To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.

Semiconductor wafer with low-K dielectric layer and process for fabrication thereof

A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.

Method of making a vertical photodetector

There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial semiconductor material is deposited over the first seed layer region. A capping layer is formed to overlie the epitaxial semiconductor material and the remaining portion of the sacrificial layer. Portions of the capping layer are removed to form a capping structure that overlies a part of the remaining portion of the sacrificial layer. Portions of the sacrificial layer not covered by the capping structure are removed to form a sacrificial structure having sidewalls. Fin structures are formed adjoining the sidewalls by depositing a semiconductor material along the sidewalls. Portions of the capping structure are removed to expose portions of sacrificial layer between adjacent fin structures. Portions of the sacrificial material between the adjacent fin structures are removed.

Semiconductor fin integration using a sacrificial fin

A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.

Forming semiconductor fins using a sacrificial fin

A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

Conductive via formation utilizing electroplating

A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.

Programmable ROM using two bonded strata

A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M&#xd7;N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M&#xd7;N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

Fabrication of three dimensional integrated circuit employing multiple die panels

A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer along a sidewall of a first opening in a first dielectric layer, located over the surface of the integrated device, and providing a deformable metal feature adjacent to the sidewall spacer and in the first opening. The method further includes providing a second integrated device having a substrate, an overlying interconnect region, a contact, and a second dielectric layer surrounding the contact of the second integrated device. The method further includes contacting the contact of the second integrated device with the deformable metal feature and pressing the first dielectric layer against the second dielectric layer.

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Austin, TX, United States of America

Robert E Jones