Agilent Technologies, Inc.

Hewlett-Packard Company

Keysight Technologies, Inc.

Robert E Jewett

Kenneth D Poulton

Nicholas Tufillaro

Jacky Kin Chi Liu

A circuit for digital-to-analog conversion includes a first digital-to-analog converter (DAC), a second DAC, and an output node. The first DAC provides charges from multiple first charge sources segmented into a first group for most significant bits of a digital input to the first DAC and a second group for least significant bits of the digital input. Dither is both added to the digital input to the first DAC and used as sole digital input to the second DAC. Analog output from the second DAC is subtracted from analog output of the first DAC at the output node so as to cancel the dither added to the first DAC.

Least significant bit dynamic element matching in a digital-to-analog converter

In one embodiment, a spectral map for performing nonlinear calibration of a signal path is developed by 1) identifying a set of frequency locations for a set of particular output signal spurs that result from applying one-tone and two-tone input signals covering a bandwidth of interest to the signal path; 2) developing, based on the set of frequency locations, a spectral map for predistorting, in the frequency domain, signals that are applied to, or received from, the signal path in the time domain; and 3) saving the spectral map for performing nonlinear calibration of the signal path.

Methods and apparatus for computing and using a spectral map for performing nonlinear calibration of a signal path

Embodiments of a reduced noise reduction system ('RNFDS') include a frequency divider and a resampler in signal communication with the frequency divider. The frequency divider receives an input signal and, in response, produces a divided signal. The input signal has a first frequency and the divided signal has a second frequency, different from the first frequency. The resampler receives the input signal and the divided signal, and resamples the divided signal using the input signal as a sampling clock signal to produce a resampled output signal. The frequency divider imposes edge jitter on the divided signal. Resampling the divided signal produces the resampled output signal with an edge jitter comparable with that of the input signal.

Reduced-noise frequency divider system

A digital-to-analog converter (DAC) and method for converting digital inputs into analog outputs utilizes resampling switches to regulate the transmission of partial analog signals between analog output elements and a summing circuit to reduce or eliminate &ldquo;glitches&rdquo; in the output signal. Each resampling switch may be individually connected to an analog output element to handle a fixed partial analog signal, e.g., a fixed current, generated by that analog output element. Consequently, the resampling switches can be used to reduce or eliminate the glitches in the output signal without introducing switch nonlinearity into the output signal by simultaneously transmitting the partial analog signals to the summing circuit using the resampling switches.

Per-element resampling for a digital-to-analog converter

The raw digital output signal generated at the transmitter by an ADC is XOR'd with a sequence of pseudo-random numbers to generate an encoded output signal. This removes all correlation between the analog input signal and the encoded output signal. Coherence between the encoded output signal and the analog input signal is prevented and the effects of crosstalk to the analog input signal are mitigated. In a first embodiment of the invention, the sequence of pseudo-random numbers is a sequence of one-bit pseudo-random numbers that are XOR'd with each bit of the raw digital output signal. In a second embodiment, the sequence of pseudo-random numbers is a sequence of N-bit pseudo-random numbers that are XOR'd with the N-bit words of the digital output signal. To recreate the original raw digital output signal in the receiver, a second XOR operation is performed between the encoded output signal and the sequence of pseudo-random numbers. Alternatively, a pseudo-random number generator located in each of the transmitter and receiver are synchronized to generate equal sequences of PRNs that encode the raw digital output signal and decode the encoded output signal. Intermediate digital pipelining may be used to add a decoding bit from the pseudo-random-number generator to the encoded output signal. Such additional bit may be stored in memory with the encoded output signal to permit later decoding.

System for preventing of crosstalk between a raw digital output signal

A broadband high frequency signal generator is disclosed having a low and a high frequency swept signal source connected to a YIG tuned frequency multiplier. One end of an output coupling loop for the YIG is connected to ground through a PIN diode, and the low frequency signal source is connected to the junction of the output coupling loop and the PIN diode. When the PIN diode is caused to conduct, signals from the high frequency source are passed through the YIG tuned multiplier to an output in the conventional manner. When the PIN diode is not conducting, signals from the low frequency source are passed to the output through the output coupling loop.

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Redwood City, CA, United States of America

Robert E Jewett