Cisco Technology, Inc.

Robert E Jeter, Jr

John William Marshall

Kenneth H Potter

Jeffery B Scott

John A Chanak

Kenneth Harvey Potter, Jr

Darren R Kerr

Manish Changela

In one embodiment, a processor is operable to issue a first memory request to access a particular memory location, and, prior to completion of the first memory request, to issue a command to release a memory lock on the particular memory location when access to the particular memory location is complete. The processor is further operable to, prior to release of the memory lock, issue a second memory request to access a different memory location. Also a memory management unit is operable to receive the command to release the memory lock and to monitor for when access to the particular memory location is complete. The memory management unit releases the memory lock in response to completion.

Memory fence with background lock release

A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory request should be issued by the local memory management unit (MMU) to a local memory, or should be transferred by the local MMU to a remote MMU and issued by the remote MMU to a remote memory, the remote memory associated with a different processor. In this manner, the remote MMU issues certain memory requests on behalf of the local processor and returns any results back to the local processor.

Full access to memory interfaces via remote request

A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.

Zero overhead resource locks with attributes

A technique for maintaining order among a plurality of entities contained in an intermediate node by ensuring orderly access to a resource shared by the entities. A request is generated to access the resource. The request is placed on a queue associated with an entity. The request eventually reaches the head of the queue. An identifier generated by a gate manager is compared with an identifier associated with the queue to determine if they match. If so, the request is transferred to the resource, which processes the request. Results acquired from the resource (if any) are transferred to the entity.

Maintaining entity order with gate managers

A technique for controlling access to resources that may be accessed by one or more entities in a system. According to the technique, an entity accesses a shared resource by issuing a request containing an identifier that identifies the resource and an operation that specifies an operation to be performed on the resource. The operation is compared with one or more outstanding operations associated with the shared resource to determine if the operation conflicts with one or more of the outstanding operations. If a conflict is detected, a guard value is applied to determine if a race condition could occur. If a race condition is detected, the operation is blocked; otherwise, the operation is allowed.

Memory controller that tracks queue operations to detect race conditions

A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

System and method for dynamic mirror-bank addressing

A technique releases locks associated with particular memory locations. The technique uses a 'background' approach to determining when the locks should be released in that memory operations associated with the memory locations are monitored while instructions continue to execute on a processor. The memory operations are monitored by generating a condition for each memory operation and clearing the condition when the operation completes. When all the conditions are cleared, the associated locks are released.

A technique for enabling a processor to access a memory not directly coupled to the processor. According to the technique, a local processor accesses a remote memory by issuing a memory request that contains an indicator that indicates the request is addressed to the remote memory. The request is then transferred to a remote memory management unit (MMU) coupled to the remote memory. The remote MMU acts as a proxy and issues the memory request to the remote memory on behalf of the local processor. The results of the request, if any, are returned to the local processor.

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Morrisville, NC, United States of America

Robert E Jeter, Jr