Intel Corporation

Robert E Gough

Barnes Cooper

David J Harriman

Jaya L Jeyaseelan

Neil W Songer

Paul S Diefenbaugh

Krishnakanth Venkata Sistla

Mahesh U Wagh

Ankush Varma

Michael A Rothman

Prashant Sethi

Mikal Hunsaker

Ilan Pardo

Mark Doran

Andrew D Henroid

Yuval Bachrach

Guy G Sotomayor

Reuven Rozic

Basavaraj B Astekar

Sean Dardis

Gideon Prat

Rafi Ben-Tal

James E Jaussi

Seh Kwa

Tod F Schiff

Maxim Dan

Jim Walsh

Mazen G Gedeon

Shanthanand Kutuva Rabindranath

Eliezer Weissmann

Kristoffer Fleming

Chia-Hung Sophia Kuo

Pronay Dutta

Nathaniel L Desimone

Ismail Ebrahim

Vincent J Zimmer

Mohan J Kumar

Efraim Rotem

Alon Naveh

Ohad Falik

Nadav Shulman

Jeremy J Shrall

Eugene Gorbatov

Guy M Therien

David W Browning

Michael Mishaeli

Sarathy Jayakumar

Nilesh V Shah

Kirk D Brannock

Anil Aggarwal

Chee Lim Nge

Karthi R Vadivelu

Jose Andy Vargas

Douglas Raymond Moran

John William Horigan

Nicholas J Adams

Neelam Chandwani

Nivedita Aggarwal

Soethiha Soe

Vasudev Bibikar

Subrata Banik

Vijaykumar Balaram Kadgi

Vinay Raghav

Venkataramani Gopalakrishnan

Bharath Kumar

Vijay S R Degalahal

Avinash P Chakravarthy

Peter A Dice

Panner Kumar

Jabeena Begum Gaibusab

Erik C Bjorge

Isaac W Oram

Uri Soloveychik

Mikal C Hunsaker

Xiang Ma

Aamir Bohra

Naveen Gopal Reddy

Sai Prasad Paithara Balagangadhara

Kristoffer D Fleming

During a computing system boot sequence, reference firmware provided by a computing system component supplies Advanced Configuration and Power Interface (ACPI) code that generates ACPI tables and definition blocks to a bootloader. During a boot sequence, the reference firmware receives an indication from the bootloader which components the reference firmware is to initialize. As part of component initialization performed by the reference firmware, the reference firmware populates hand-off data structures (e.g., hand-off blocks (HOBs)) with ACPI code (AML code) that, when executed by the bootloader, generates and populates ACPI tables (e.g., DSDT and SSDT tables) and definition blocks with information pertinent to the initialization and runtime management of computing system components. Component initialization and runtime configuration workarounds can be implemented in the bootloader incorporating reference firmware updates provided by the component vendor.

Platform hardening for bootloaders via reference firmware

A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

Flattening portal bridge

Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.

Power management of discrete communication port components

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

Dynamically updating logical identifiers of cores of a processor

Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.

Automatic switching and deployment of software or firmware based USB4 connection managers

In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Computing performance and power management with firmware performance data structure

In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

System, apparatus and method for collective power control of multiple intellectual property agents and a shared power rail

An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

Electronic device having a controller to enter a low power mode

A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.

Method and apparatus to reduce idle link power in a platform

An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.

Downstream device service latency reporting for power management

A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints

A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

Growing community of inventors

Sherwood, OR, United States of America

Robert E Gough