Other

Boost Ideas, LLC

Motorola Corporation

Robert E Garner

Paul R Metcalfe

Scott E Urban

Alexis Hornstein

Nathaniel Sharpe

James Loy Brewster

David Neal Gardner

Heather Brundage

Robert Bradford Cohen

David Shao Ling

Anna Elman

Mark Alan McAdams

Alvaro Eduardo Benavides

Jeffrey Jussel

James Brewster

A water safety garment and apparatus configured to avoid drowning can be configured to permit submergence for a predetermined period of time without inflation. After the predetermined time has passed, the garment or other apparatus can be configured to inflate to help a person wearing the garment float on top of the water to avoid drowning or other potentially harmful condition that may result from being underwater for too long. In some embodiments, a circuit may be utilized to detect the submergence condition of a person wearing the apparatus or garment. Upon a determination that the detected submergence condition has occurred continuously for a pre-determined period of time, an inflation mechanism can be actuated to force the person wearing the apparatus or garment to float to the top of the water.

Water safety garment, related apparatus and methods

A helicopter dolly includes a platform defining a helicopter landing area, a plurality of rollers connected to the platform such that a vertical clearance is defined between the platform and the ground and a plurality of safety panels movably connected to edges of the platform so as to be movable relative thereto between raised and lowered positions. The safety panels cover the vertical clearance in the lowered position. A method of using a helicopter dolly includes arranging a helicopter dolly for a helicopter landing, moving a plurality of safety panels and a plurality of corner members to cover a vertical clearance defined between a platform and the ground and moving the plurality of safety panels and the plurality of corner members to uncover the vertical clearance after the helicopter landing.

Helicopter dolly

A full mouth toothbrush for simultaneously brushing the facial, lingual, occlusal and incisal surfaces of all the maxillary and mandibular teeth is provided. The full mouth toothbrush can include a handle, a power source, a motor assembly, and a drive assembly. The full mouth toothbrush can further include a mouthpiece configured to collectively contact multiple surfaces of multiple teeth simultaneously that brushes and, thus, cleans the teeth and gums.

Teethbrush

A device and method for brushing all surfaces of all of a user's teeth simultaneously. The device comprises bristle strip surfaces that envelope all of a user's teeth, the bristle strips comprising bristle bundles that scrub all surfaces of a user's teeth due to a reciprocating motion of the bristle strips. To use the device, a user inserts the toothbrush bristle strips into their mouth so to engage the user's teeth. A power source, motor, and drive assembly are utilized to cause the bristles to reciprocate, cleaning all a user's teeth surfaces simultaneously.

Apparatus and method for brushing teeth

The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component types. Instantiated components versions comprise 'deliverables' and 'attributes.' Deliverables comprise a file or directory of files or groups of files or directories that perform a common function and are characterized by the system in a standardized manner. Attributes comprise metadata describe the component version. By the abstraction of design files into deliverables, the systems can work with design files originating from any source and having different structures and still make those design files available by other designers in a uniform manner for efficient reuse of pre-qualified components. Tasks in the design flow can be tracked in the system. The system may also include a communications application, an issue tracking application, and an audit trail application.

System for intellectual property reuse in integrated circuit design

A method and apparatus for socket-based design with reusable intellectual property (IP) includes a chip integration system (CIS) that provides designers with a convenient method to create and describe a system on a chip (SOC) design independent of design flow. A Chip Integration Description Language (CIDL) is also disclosed that provides a mechanism for defining interfaces between IP cores in a way that isolates a system designer from much of the connection information previously required is also disclosed. Using CIDL, a system designer is able to rapidly connect multiple blocks of intellectual property (IP) based upon the functionality of the blocks rather than traditional hardware-specific connection methods. The details pertaining to specific connections that may be needed are encapsulated within a CIDL-based file that is typically written by the IP core designer. The actual connection of signals between blocks of IP, however, is performed by a CIDL compiler that uses the CIDL file(s) as input.

Method and apparatus for socket-based design with reusable-IP

A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.

Single-chip microcontroller with efficient peripheral testability

A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.

Growing community of inventors

Austin, TX, United States of America

Robert E Garner