Tracor, Inc.

Galaxy Microsystems, Inc.

Robert E Fosdick

A microprocessor that detects and corrects random soft errors during program execution occurring in its storage elements (memory). Such a microprocessor utilizes a bit serial architecture and single error correction double error detection techniques that automatically detect and correct soft errors occurring in its internal memory elements during each word cycle. The microprocessor automatically detects and corrects soft errors during each word cycle. The error detection and correction is transparent to the external microprocessor interface. The microprocessor also utilizes a multi-level hierarchical structure which maintains a high instruction execution throughput and also minimizes the number of transistors required for its implementation.

Error tolerant microprocessor

A microcoded central processing unit (CPU) is used to emulate the macroinstructions of a target computer. Each macroinstruction emulated is divided into two phases, an operand derivation or classification phase and an instruction execution phase. A microcontroller is provided to control each of the two separate phases. The two microcontrollers operate in parallel and simultaneously in performing their respective operations. The two microcontrollers are synchronized together so that when one microcontroller needs access to CPU resources that are currently under control of the opposite controller, the requesting microcontroller is put to sleep until the needed resource comes available before it continues its operations. Microcode is minimized by sectionalizing the micromemory such that certain microcode can be shared by both microcontrollers where common microcode is needed to emulate different macroinstructions. A three section micromemory is provided with the right section normally associated with the operand derivation, the left section associated with the instruction execution, and the middle micromemory available to either microcontroller. Either microcontroller may specify the address of any one of the three sections in micromemory. As a result of the manner in which the middle memory is shared by the microcontrollers, when a phase requires resources controlled by the commonly used microcode, those resources can be obtained without necessarily having to stop the operation of the other microcontroller. Throughput of the emulator is thereby increased. The emulator also includes an interrupt unit for handing a priority system of peripheral interrupt requests.

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Austin, TX, United States of America

Robert E Fosdick