Ncr Corporation

Robert E Enfield

Robert G Fulks

Eric Sacher

Edward H Greenwood

A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature file containing known correct signatures for the nodes of a board under test and also stores an image file which contains information defining the topology of the board under test. The driver/sensor circuits are programmable to receive test information generated by a test program stored in the main memory, transmit such information to inputs of a board under test, and receive information produced by the board under test in response to the input test information. The response received from outputs of the board under test is compared to a corresponding known-correct response to identify a faulty output of the board under test. The processor refers to the image file to identify a logic element driving the faulty output and to identify the nodes which are inputs to the logic element. The processor causes instructions to be displayed to the operator of the portable digital tester to instruct the operator to probe the input nodes of the logic element. A signature is generated for each node and compared to a corresponding known correct signature for that node as it is probed by the operator to identify a faulty input node. For each faulty node found, the measured signature, the initial state, and a number equal to the smaller of an input test number of the known correct initial transition of the faulty node and an input test number of the first incorrect transition of the faulty node is stored in a history file having pointers to the image file for each node. If a component is found having a faulty output and all good inputs, that component is identified as defective. If a loop is identified by the main processor, the operator is instructed to test all external inputs to the loop; if a faulty external input is found, the loop is resolved, and the processor instructs the operator to probe another node. If the external inputs are all good, the main processor scans the history table to determine which node in the loop failed first and indicates that the component driving that node is the probable fault.

Method and apparatus for isolating faults in a logic circuit

Portable tester and method for testing a variety of circuit boards without utilizing adaptor boards for re-routing input test signals and supply voltage from the tester to pins of the board under test. A plurality of edge adaptors having different pin spacings have their respective pins connected in parallel to corresponding edge connector stake pins. Each edge connector stake pin is connected to or isolated from the corresponding driver/sensor stake pin by means of a switch. Each driver/sensor stake pin is connected to the input/output terminal of a programmable driver/sensor circuit. A plurality of power supply stake pins are connected to various power supplies of the portable tester. Connectors coupled to the family board can be utilized to route power supply voltages to electrically isolated edge connector stake pins. Isolated driver/sensor outputs can be routed to other edge connector stake pins. A main processor stores a test program and transmits data and control information to predetermined driver/sensor circuits. A high speed processor is coupled between the main processor and the inputs of the driver/sensor circuits. The high speed processor memory can store a bus-defining subroutine containing a sequence of data shifting instructions which shift a word in the shift register to the input of specified driver/sensor circuits at high speed. The high speed processor can synchronize the operation of the portable tester with an asynchronously operating printed circuit board under test.

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Phoenix, AZ, United States of America

Robert E Enfield