Xilinx, Inc.

Robert E Eccles

Austin H Lesea

Mark Brian Roberts

Method and apparatus for design verification with equivalency checking is described. More particularly, an integrated circuit design for a device having programmable logic is obtained, and a test case design having one or more test patterns is obtained to test the integrated circuit design. Memory states for the test patterns are obtained and applied to configure at least a programmable logic portion of the integrated circuit design with at least one test pattern to provide a configured design. Equivalency checking with the at least one test pattern and the configured design may be done to determine if the configured design is functionally equivalent to the at least one test pattern.

Method and apparatus for design verification with equivalency check

Method and apparatus are described for providing a rule file. More particularly, a design rule document is converted to a table file of design rules and associated design rule values, where design rules follow a naming convention to maintain uniqueness among them. A parameterized design rule check (PDRC) file is obtained. Such a PDRC file calls out design rule names instead of design rule values. A computer program is used to exchange design rule values associated with design rule names in the table file for the design rule names called out in the PDRC file to provide a design rule check (DRC) file. This method and apparatus also apply to any technology file containing parameterized rules.

Method and apparatus for rule file generation

Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

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San Jose, CA, United States of America

Robert E Eccles