Freescale Semiconductor,inc.

Motorola Corporation

Robert E Booth

Jinbang Tang

Marc Alan Mangrum

Kenneth R Burch

Darrel R Frear

Jong-Kai Lin

Lawrence N Herr

Mahbub M Rashed

Sushama Davar

Giri Nallapati

Michael P Woo

Douglas J Dopp

Robert Arthur Rodriguez

Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Method of making an integrated circuit package with shielding via ring structure

A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Hybrid transistor based power gating switch circuit and method

Electromagnetic shield formation for integrated circuit die package

A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Programmable bias for a memory array

A method for manufacturing an static random access memory (SRAM) cell (10) begins by manufacturing a fuse region (36) over a substrate (10). An etch stop layer (44) is formed overlying the fuse region (36) from resistor polysilicon material. In order for the fuse region (36) to be accessed and properly disabled, an opening (60) must be provided which stops on the etch stop layer (44). The etch stop (44) ensures a consistent and repeatable optimal thickness X of dielectric material above the fuse region (36) to provide for proper laser access and repair. The etch stop layer (44) therefore reduces wafer to wafer and die to die variation in thickness X and provides for a higher yield laser repair for each SRAM integrated circuit and every wafer processed using this methodology.

Method for forming a laser alterable fuse area of a memory cell using an

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Austin, TX, United States of America

Robert E Booth