International Business Machines Corporation

Other

Endicott Interconnect Technologies, Inc.

Robert Douglas Edwards

Voya Rista Markovich

James Warren Wilson

John Joseph Konrad

John Gerard Gaudiello

Jeffrey Alan Knight

Timothy Leroy Wells

Allen Frederick Moring

Gerald L Ballard

Frank Daniel Egitto

George Frederick Walker

Anilkumar Chinuprasad Bhatt

Jerzy Maria Zalesinski

Roy H Magnuson

David Erle Houser

Anthony P Ingraham

Michael Wozniak

Thomas P Gall

Jaynal Abedin Molla

James Steven Kamperman

Norman A Card

Richard Stuart Zarr

Paul Joseph Hart

Richard Gerald Murphy

A Earl Smith

Leo Raymond Buda

Bette Jaye Whalen

Warren R Wrenner

Paul S Gursky

Edmund Glenn Benjamin

Biebele Opubo Benebo

George John Saxenmeyer, Jr

A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.

Plating method for circuitized substrates

Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.

Structure having embedded flush circuitry features and method of fabricating

A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

Method and apparatus for in-situ testing of integrated circuit chips

Gold is deposited on a copper base defining electrical circuit features disposed on a substrate containing a palladium seeder, by initially treating the substrate with an alkaline cleaner, followed by treating the substrate with sodium persulfate, and subsequently treating the substrate with a diluted sulfuric acid solution. The substrate is rinsed between each one of the treatments, and after the final rinse following treatment with diluted sulfuric acid, the substrate is immersed in a gold deposition solution whereby gold is deposited on the exposed surfaces of the copper circuit features on a substrate. The process embodying the present invention provides a method for depositing gold on high density copper conductor lines or pads, even in areas of the surface in which the conductors are spaced apart 2.0 mil or less, without cleaning or removing the palladium seed from the surface.

Method for electroless gold deposition in the presence of a palladium seeder and article produced thereby

Method for electroless gold deposition in the presence of a palladium

Electrodepositing a metallurgy such as gold on to printed circuit board features. The methods include electrolessly depositing a copper layer over the surface of the printed circuit board. This is followed by applying a layer of photoresist atop the electroless copper, and exposing and developing the photoresist to uncover areas to be etched, leaving behind the specific features to be plated. By this expedient the remaining copper forms a commoning layer. The remaining photoresist is stripped to uncover the copper commoning layer, and a second layer of photoresist is applied atop the partially etched copper layer. This layer of photoresist is exposed and developed to uncover the features to be plated. These features are then plated with the metallurgy of choice. The photoresist is then stripped off and the electroless copper layer can remain if needed for further processing or be microetched off without harming copper traces that may exist below the electroless copper layer.

Electrolytic method of depositing gold connectors on a printed circuit

Disclosed is a method of producing vias and through holes through a metal laminate. The laminate is a multi-layer, for example, a trilayer of a relatively hard metal between two layers of a relatively soft metal. The method includes the steps of first etching a clearance hole through the soft metal on one side of the trilayer laminate, followed by partially etching the hard metal layer. Next, drilling the remaining thickness of the hard metal, and drilling through the second layer of soft metal.

Method of drilling vias and through holes

The present invention entails an automatic soil sampling machine that is pulled through the field by a prime mover. A disk is utilized and is power driven by an internal combustion engine or other power source. About the outer circumference of the disk there is provided structure that effectively engages the soil as the disk is powered therethrough and flings the soil upwardly out of the ground into a rooster tail airborne configuration. A catching basket or container is mounted on the soil sampling machine and catches the soil particles being flung from the ground.

Automatic soil sampling machine

Growing community of inventors

Binghamton, NY, United States of America

Robert Douglas Edwards