Micron Technology Incorporated

Robert Douglas Cassel

Srivatsan Venkatesan

Sundaravadivel Rajarajan

Iniyan Soundappa Elango

Koushik Banerjee

Jason R Johnson

William L Cooper

Isaiah O Gyan

Jian Jiao

Michael P O'Toole

Chandrasekhar Mandalapu

Sateesh Talasila

Michael P O'TOOLE

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

Spike current suppression in a memory array

Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Configurable resistivity for lines in a memory device

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.

Charge screening structure for spike current suppression in a memory array

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.

Access line having a resistive layer for memory cell access

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells. To reduce electrical discharge associated with current spikes, a first resistive film is formed in the access line between the left portion and the conductive layer, and a second resistive film is formed in the access line between the right portion and the conductive layer.

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Lehi, UT, United States of America

Robert Douglas Cassel