Lenovo (Singapore) Pte. Ltd.

Robert Diokno

Paul Daniel Kangas

Michael D French

Timothy M Wiwel

Timothy R Tennant

Matthew Weber

A memory system for a computer is provided as well as a method for integrity testing a memory interface. The memory system includes a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output. The memory system further includes an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to one of the plurality of inputs of the AND gate. The method includes driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes, and determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.

Memory system for rapidly testing data lane integrity

An edge connector socket is configured to receive an edge connector on a memory module. A wedge member is slidably secured within the edge connector socket in alignment between contacts on the edge connector and pins within the edge connector socket. A cam is rotatably secured adjacent the wedge member, and an actuator is coupled to the cam. Rotation of the cam moves the wedge member between a first position and a second position. In the first position, the wedge member is disposed between the contacts and the pins and prevents engagement between the contacts and the pins. In the second position, the wedge member is withdrawn from between the contacts and the pins and allows reengagement between the contacts and the pins. Optionally, such a 'reseat' action is performed in response to detecting an error associated with the memory module.

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Raleigh, NC, United States of America

Robert Diokno