Ford Motor Company Limited

Robert Dennis Crawford

Bradley Earl BeMent

Donald Charles Franks

Jack R Volk

Kevin Mark Tiedje

Wayne J Johnson

Douglas Nolff

Michael Lee Javernick

Theo Kimber, Jr

A method and circuit for receiving frame messages connected to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communication system. The method includes the steps of: (a) receiving the type and target bytes, and responsive thereto generating a first interrupt signal to the microcontroller at the node; (b) commanding the microcontroller, responsive to receiving the first interrupt signal, for qualifying the frame message by retrieving and matching one or more of the type and target bytes with corresponding bytes stored in programmable memory within the microcontroller, and responsive thereto generating a qualified signal; and (c) receiving data bytes from the frame message only responsive to receiving the qualified signal from the microcontroller.

Half-message based multiplex communication interface circuit which uses

A method or protocol for generating an Interrupt Signal for communication between a peripheral device and a host processor having either a level-sensitive or an edge-sensitive interrupt detector. After receiving an active interrupt request, and after confirming that the Chip Select signal is released, the interrupt signal is transitioned to an active level. After receiving an active Chip Select signal and multiple Clock pulses from the host as confirmation of receipt of the Interrupt Signal, the Interrupt Signal is transitioned to its inactive state. If the interrupt request is still pending, and when the Chip Select signal is released, then the Interrupt Signal is again made active. Maintaining the active level for the Interrupt Signal until the confirmation is returned from the host will activate level-sensitive detectors, while edge-sensitive detectors in the host will be activated by the multiple transitions ocurring if the host does not service the interrupt request in the peripheral.

Method for providing both level-sensitive and edge-sensitive interrupt

A method is provided for serial communication between a host device and a peripheral device. The method includes transmitting an interrupt command from the host to the peripheral in response to a peripheral interrupt signal and, substantially simultaneously, transmitting interrupt status data from the peripheral to the host, the interrupt status data representing a pending peripheral interrupt and indicating whether a communication error has occurred. The method also includes transmitting a continue code from the host to the peripheral based on the interrupt status data and, substantially simultaneously, transmitting information associated with the pending interrupt from the peripheral to the host in response to the interrupt command, the information having a predefined structure based on the interrupt status data for use in resolution of the pending interrupt. A system is also provided for performing the method.

Method and system for serially based host/peripheral communication

A method for detecting fault conditions on a multiplexed network having first and second busses. The method includes sensing a start of frame delimiter (SOF) for the first bus, and determining the state of the second bus when the SOF is sensed. If the state of the second bus has been passive over a first selected time period, the state of a differential between the first and second busses is determined. If the state of the differential between the first and second busses is not indicative of a pre-qualified start of frame delimiter, then a passive fault is indicated. Additionally, the method includes sensing an end of frame delimiter (EOF) for the first bus, and determining the state of the second bus when the EOF is sensed. If the state of the second bus has been active over a selected time period, then an active fault for the second bus is indicated. A system for performing the method is also disclosed.

Method and system for detecting fault conditions on multiplexed networks

A Class A node comprising a slave bus controller circuit (SBCC) operates as a remote input/output device for performing Class A communications for a master Class B node over an interconnecting SAE J1850 or similar network. The SBCC receives messages from one or more Class B nodes to receive output data which appears at one or more output ports of the SBCC. Output data may be directly provided or may be combined with mask data such that only mask selected bits of the output data are passed to the one or more output ports of the SBCC. Input data directly connected to one or more input ports of the SBCC are transmitted back to a master node as an in-message response of the network. The SBCC provides inexpensive Class A communications using the SAE J1850 protocol which is primarily intended for Class B communications. The SBCC is inexpensive because of its simplified circuitry, its ability to operate without a controlling processor and, in some embodiments, the implementation of its master clock as a RC oscillator which does not directly determine bit timing for the SBCC but is used to measure the bit timing of the master node from which it is receiving messages.

Slave bus controller circuit for class A motor vehicle data

A data transfer communication system capable of handling both node-to-node data transfer messages originating at any transmitter and transmitted to a specific receiver on the network and functional command messages originating at any transmitter and broadcast transmitted to an unspecified number of receivers on the network. Receivers are programmed to receive and acknowledge receipt of correspondingly addressed node-to-node type messages and certain correspondingly addressed functional command type messages with their unique addresses in a predetermined field location of the transmitted message. By utilizing pulse width modulation techniques, binary logic signals and a unique start signal are defined and have a dominant hierarchy that allows for bit-wise contention of the common data bus. In that manner, when contention of the data bus is resolved a higher priority message continues to be transmitted while losing contender delays its transmission until after the higher priority message is completed.

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Livonia, MI, United States of America

Robert Dennis Crawford