Sandisk Technologies Inc.

Sandisk Il Ltd.

Hitachi Global Storage Technologies Netherlands B.v.

Robert David Selinger

Paul A Lassa

Gary Lin

Chaoyang Wang

Eli Harari

Menahem Lasser

Alan Welsh Sinclair

Ori Stern

Sandra Almog Goldschmidt

Richard R Heye

The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

Method and controller for performing a sequence of commands

The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

Method and controller for performing a copy-back operation

A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command.

Controller and method for using a transaction flag for page protection

A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address.

Controller and method for memory aliasing for different flash memory types

The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

Controller, storage device, and method for power throttling memory operations

The embodiments described herein provide methods for executing a command to write data from a source location to a destination location in a memory device. In one embodiment, a memory device receives, from a host device, a command to write data from a source location to a destination location in the memory device. The memory device executes the command by changing the memory device's logical-to-physical address map without reading the data from the source location and writing the data to the destination location and without a need of further involvement of the host device after the host device sends the command to the memory device.

Methods for executing a command to write data from a source location to a destination location in a memory device

A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

NAND flash memory controller exporting a NAND interface

An electronic memory module according to the invention provides non-volatile memory that can be used in place of a DRAM module without battery backup. An embodiment of the invention includes an embedded microprocessor with microcode that translates the FB-DIMM address and control signals from the system into appropriate address and control signals for NAND flash memory. Wear-leveling, bad block management, garbage collection are preferably implemented by microcode executed by the microprocessor. The microprocessor, additional logic, and embedded memory provides the functions of a flash memory controller. The microprocessor memory preferably contains address mapping tables, free page queue, and garbage collection information.

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San Jose, CA, United States of America

Robert David Selinger