International Business Machines Corporation

Auriga Innovations, Inc

Robert Daniel Edwards

Ping-Chuan Wang

Oleg Gluschenkov

Ronald G Filippi

Kaushik Chanda

Yongchun Xin

Tso-Hui Ting

Louis V Medina

Andrew Herbert Simon

Griselda Bonilla

Hazara Singh Rathore

Chih-Chao Yang

Lawrence Alfred Clevenger

Jeffrey P Gambino

Hariklia Deligianni

Jonathan David Reid

Richard Paul Volant

Robert Allen Groves

Edward William Kiewra

Bernd Karl Appelt

Thomas J Fleischman

Paul Stephen McLaughlin

Kimball M Watson

Roy Charles Iggulden

Du Binh Nguyen

Perminder S Bindra

Charles F Musante

Jae M Park

Andrew P Cowley

Charles J Montrose

Richard G Smith

J Edwin Hostetter

James R Loomis

Conrad A Barile

James R White

James Joseph Poulin

Lisa J Smith

Robert Edgar Davis

A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

Semiconductor wafer probing system including pressure sensing and control unit

An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Interconnect structure with enhanced reliability

Pressure sensing and control for semiconductor wafer probing

A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.

Reliable back-side-metal structure

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

Method for prediction of premature dielectric breakdown in a semiconductor

One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.

Edge seal for thru-silicon-via technology

The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems

The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

Process of enclosing via for improved reliability in dual damascene interconnects

A test socket is provided as part of a high temperature electromigration test system to allow the prediction of median time to failure to temperatures in excess of 450.degree. C. of VSLI interconnects.

High temperature electromigration stress test system, test socket, and

Substantially nonconductive or semiconductive surfaces of through holes can be electroplated directly, without an intervening non-electrolytic metallization, by a stepwise process which includes the application to the through holes of a polyelectrolyte surfactant in solution in combination with the application of a conductive metal containing material.

Direct electroplating of through holes

Growing community of inventors

Marlboro, NY, United States of America

Robert Daniel Edwards