Interval Research Corporation

Tyzx, Inc.

Intel Corporation

Apple Inc.

Vulcan Patents LLC

Robert Dale Alkire

Henry Harlyn Baker

John Iselin Woodfill

Brian Von Herzen

Steven E Saunders

Michael Naimark

Robert L Adams

David J Gessel

Christoph Dohrmann

Louis F Roehrs

A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.

Generation of a disparity result with low latency

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) andstatic random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

Data processing system and method

Disclosed is an input device and method for interacting with motion pictures incorporating content-based haptic response. Content data relating to the motion picture is stored in a content data storage device while motion picture data is stored in a prerecorded image data storage device. A viewer input device is provided so that a viewer (end-user) can advance and reverse the frames on a display screen while substantially simultaneously, the content data is accessed and braking commands are sent to the viewer input device. The result is that the viewer is provided with haptic responses to the viewer's input through the viewer input device.

Input device for controlling a video display, incorporating

An input device and method for interacting with motion pictures incorporating content-based haptic response is provided. Content data relating to the motion picture is stored in a content data storage device while motion picture data is stored in a prerecorded image data storage device. A viewer input device is provided so that a viewer (end-user) can move forwards and backwards through the frames on a display screen while substantially simultaneously, the content data is accessed and braking commands are sent to the viewer input device. The result is that the viewer is provided with haptic responses to the viewer's input through the viewer input device.

Input device and method for interacting with motion pictures

A multi-board computer system is described which comprises a main circuit board, a first circuit board having a third surface and a fourth surface opposite the third surface, and a second circuit board having a fifth surface. The main circuit board further includes means for generating a first board select signal to select the first circuit board and a second board select signal to select the second board. The first circuit board further includes a first input pin and a second input pin on the third surface, and a first output pin on the fourth surface. The first input pin corresponds to the first output pin. The first input pin is coupled to receive the first board select signal, and the second input pin is coupled to receive the second board select signal. The first circuit board is selected when it receives the first board select signal at the first input pin. The second circuit board further includes a third input pin. The third input pin is coupled to the first output pin of the first circuit board. The second circuit board is selected when it receives the second board select signal at the third input pin. The first circuit board further includes position shifting means for coupling the second board select signal from the second input pin of the first circuit board to the first output pin of the first circuit board. When the second input pin of the first circuit board receives the second board select signal, the position shifting means couples the second board select signal to the third input pin of the second circuit board via the first output pin. A method of selecting a circuit board in the multi-board computer system is also described.

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San Jose, CA, United States of America

Robert Dale Alkire