Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Robert D Snyder

Dean T Lindsay

Benjamin Dodge

Ian P Shaeffer

Kent Andrew Dickey

Karen Lo

A method and system allows multiple compute elements to independently read and clear error register logs, discard invalid data and ensure that a user receives information stored in error log registers. Error log registers are not cleared until its information is successfully retrieved by a compute element. A counter maintains a count of errors for which detailed error information has been lost.

Method for and system producing shared usage of intercommunication fabric error logging registers in a multiprocessor environment

Methods and apparatus for halting the data strobes transmitted over a source synchronous link to enable the data stored in the data capture flip-flops in a source synchronous receiver to be scanned out for subsequent analysis. This allows for the evaluation of the captured data without placing additional components in the functional data path and, therefore, without increasing the latency of the transmission. To provide optimal timing margins the data and data strobe paths are logically and electrically matched. This includes routing the data and data strobe signals in close proximity from the transmitter to the receiver, and through the same logical and physical elements in the transmitter and receiver. This insures that any injected link noise is experienced common-mode. In addition, the data strobe signal is preferably driven at one-half of the period of the data signal so that the data strobe and data signals experience logical state transitions at the same time and at the same frequency. This insures maximally similar electrical modes on the communication link, further maximizing link margin.

Halting data strobes on a source synchronous link and utilization of same to debug data capture problems

A method and apparatus for providing a synchronization mechanism to control accesses to a non-cached shared resource by devices connected by a high speed interconnect is herein described. A semaphore is used to control access to a shared resource which is implemented by a pair of semaphore registers. A previous semaphore register is used to store the previous owner of the semaphore and a current semaphore register is used to either store the current owner of the semaphore or indicate that the semaphore is available. The current semaphore register is updated when the semaphore is available and is being taken or when the semaphore is being freed. The previous semaphore register is updated when the semaphore is freed.

Apparatus and method for synchronizing multiple accesses to common resources

A data switch is configured to communicate data messages in the form of multibit data unit segmented into a plurality of multibit data subunits. The data switch includes at least two separate, parallel switching units, each having a plurality of ports to communicate the multibit data subunits. Hardwired or software implemented prioritization logic provides for the initiations of transfer of data messages between the ports in response to a category of the data messages. A memory is used to store a history of prior data message transfers so that least recently transferred message types are serviced prior to those most recently switched. So as to reestablish synchronization between the parallel switching units, such as loss of a data subunit, a controller responds to a reset condition by temporarily suspending communications between affected ones of the ports and clearing the history so to recommence lock-step operations of the units.

Algorithm for resynchronizing a bit-sliced crossbar

A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (&ldquo;GFC&rdquo;) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed

A system and method of mapping a network topology in a network including a plurality of nodes which communicate over dedicated links which connect pairs of the nodes, where the method consists of the steps of exchanging respective network identification information between adjacent pairs of nodes, establishing communications with another of the nodes using the network identification information, obtaining network identification information of the other node from that node, using the network identification information to establish communications with other nodes, obtaining additional network identification information from those other nodes, repeating these steps until network identification information is obtained from all of the nodes of the network and using this information determine the network topology.

Protocol for identifying components in a point-to-point computer system

A system and method for observing bi-directional information transmitted between two integrated circuits is disclosed. The bi-directional information is transmitted on first and second communication links between a first and a second integrated circuit. The second integrated circuit includes a first data port electrically coupled to the first and second communication links. A second data port of the second integrated circuit is electrically coupled to the first communication link at the first data port of the second integrated circuit. The second data port is capable of electrical connection with an analyzing device. A third data port of the second integrated circuit is electrically coupled to the second communication link at the first data port of the second integrated circuit. A third communication link electrically couples the third data port of the second integrated circuit to a first data port of a third integrated circuit. A second data port of the third integrated circuit is electrically coupled to the first data port of the third integrated circuit, the second data port capable of electrical connection with the analyzing device.

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Ouistreham, France

Robert D Snyder