California Institute of Technology

The United States of America As Represented by the Administrator of the

Robert D Rasmussen

Robert M Manning

Erann Gat

Douglas J Sheldon

Huy H Luong

Savio N Chau

Eddy Shalom

Blair F Lewis

Kim P Gostelow

Richard S Ward

Robert M Keller

Chester J Everline

Thomas W Starbird

Daniel L Dvorak

Paul N Bowerman

Steve Ankuo Chien

Leonard Day

Timothy L Heaps

Ryan Fukuhara

Gary S Bolotin

Systems and methods for estimating the lifetime of an electrical system in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes iteratively performing Worst Case Analysis (WCA) on a system design with respect to different system lifetimes using a computer to determine the lifetime at which the worst case performance of the system indicates the system will pass with zero margin or fail within a predetermined margin for error given the environment experienced by the system during its lifetime. In addition, performing WCA on a system with respect to a specific system lifetime includes identifying subcircuits within the system, performing Extreme Value Analysis (EVA) with respect to each subcircuit to determine whether the subcircuit fails EVA for the specific system lifetime, when the subcircuit passes EVA, determining that the subcircuit does not fail WCA for the specified system lifetime, when a subcircuit fails EVA performing at least one additional WCA process that provides a tighter bound on the WCA than EVA to determine whether the subcircuit fails WCA for the specified system lifetime, determining that the system passes WCA with respect to the specific system lifetime when all subcircuits pass WCA, and determining that the system fails WCA when at least one subcircuit fails WCA.

Systems and methods for circuit lifetime evaluation

An autonomous controller, comprised of a state knowledge manager, a control executor, hardware proxies and a statistical estimator collaborates with a goal elaborator, with which it shares common models of the behavior of the system and the controller. The elaborator uses the common models to generate from temporally indeterminate sets of goals, executable goals to be executed by the controller. The controller may be updated to operate in a different system or environment than that for which it was originally designed by the replacement of shared statistical models and by the instantiation of a new set of state variable objects derived from a state variable class. The adaptation of the controller does not require substantial modification of the goal elaborator for its application to the new system or environment.

Adaptable state based control system

In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, cyclic redundancy check (CRC), and byte count check operations. The I2C bus controller may include a control unit connected to an I2C core module having a base address. The I2C bus controller may also include a second I2C core module having a base address plus one (BP ). The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or, in the master mode, from itself through the BP I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus. The control unit may format CRC values and byte count values into messages, and include a byte counter to compare actual bytes received to the expected byte count indicated by a received byte count value.

I2C bus protocol controller with fault tolerance

This is a distributed computing system providing flexible fault tolerance; ease of software design and concurrency specification; and dynamic balance of the loads. The system comprises a plurality of computers each having a first input/output interface and a second input/output interface for interfacing to communications networks each second input/output interface including a bypass for bypassing the associated computer. A global communications network interconnects the first input/output interfaces for providing each computer the ability to broadcast messages simultaneously to the remainder of the computers. A meshwork communications network interconnects the second input/output interfaces providing each computer with the ability to establish a communications link with another of the computers bypassing the remainder of computers. Each computer is controlled by a resident copy of a common operating system. Communications between respective ones of computers is by means of split tokens each having a moving first portion which is sent from computer to computer and a resident second portion which is disposed in the memory of at least one of computer and wherein the location of the second portion is part of the first portion. The split tokens represent both functions to be executed by the computers and data to be employed in the execution of the functions. The first input/output interfaces each include logic for detecting a collision between messages and for terminating the broadcasting of a message whereby collisions between messages are detected and avoided.

Distributed computing system with dual independent communications paths

Growing community of inventors

Monrovia, CA, United States of America

Robert D Rasmussen