Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Robert D Odineal

Michael L Ziegler

William R Bryg

James B Williams

Thomas R Hotchkiss

Craig R Frink

Robert J Brooks

John L Wood

Kenneth K Chan

Naysen J Robertson

Stephen B Lyle

Brendan A Voge

Robert E Naas

Joseph Hani Hassoun

Dave W Paulson

Robert N Barry

A system includes a first physical chassis comprising a first chassis management unit ('CMU'). The first CMU is configured to communicate with a second CMU in an additional physical chassis. The first CMU is also configured to communicate for the first physical chassis and the additional physical chassis as one logical chassis.

Physical chassis as a different number of logical chassis

A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Queue-based predictive flow control mechanism with indirect determination of queue fullness

Queue-based predictive flow control mechanism

A shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories. The main memory controller for each main memory of the system maintains a duplicate cache tag array containing current information on the status of data lines from the main memory that are stored in the cache memories. Thus, coherency checks can be performed directly by the main memory controller. This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.

Cache tag system for use with multiple processors including the most

A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

Multiprocessor system for maintaining cache coherency by checking the

A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

Fast pipelined distributed arbitration scheme

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Roseville, CA, United States of America

Robert D Odineal