Cyrix Corporation

Robert D Maher, Iii

John K Eitrheim

Thomas B Brightman

John R Kuban

Fred Dunlap

Patrick Antaki

A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients using 2n bit dividends and n bit divisors. Each interative division step, an adder/subtractor is used to add/subtract the properly aligned divisor to/from the left shifted dividend, to produce a partial remainder and a carry out bit Cout. Complement Cout is assumed to be the same as the most significant bit of the partial remainder PR(MSB), such that PR(MSB) is used as the sign bit in further computations, with complement Cout being used to control quotient generation according to DVRS XOR Cout. The anomalous overflow test signals overflow when complement Cout is the different than the most significant bit of the first partial remainder PR1(MSB), such that the anomalous overflow test is implemented according to the logic equation: Cout XNOR PR1(MSB).

Detecting overflow conditions for negative quotients in nonrestoring

A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first and second clocks are alternately enabled by a control signal initiated under program control of the external test system.

Testing architecture with independent scan paths

A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

Coprocessor interface supporting I/O or memory mapped communications

A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.

Normalization estimator

An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) performs a three-bit overlapping scan of the signed digit differene to determine a bit location which corresponds to the approximate bit position of the most significant non-zero bit in the result of the arithmetic process performed in adder/rounder circuit (20). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue. The number of leading zeroes is output to a barrel shifter (16) via an L-bus (30). The operands are simultaneously substracted in adder/rounder circuit (20) and the result is input into barrel shifter (16) via an M-bus (12). The result is then shifted in barrel shifter (16) according to the leading zero count input by leading zero counter (18). The shifted result is then input into a conditional shifter (18) which outputs the normalized result for subsequent rounding procedures and two's complement conversion.

Circuit for simultaneous arithmetic calculation and normalization

A bidirectional variable bit shifter (10) is disclosed which comprises a latch/input driver (12) coupled to a word shift array (14) coupled to a nibble shift array (16) coupled to a bit shift array (18) coupled to a latch/output driver (20). The bidirectional variable bit shifter (10) further comprises three sense amps (24, 26, 28) coupled to the word, nibble and bit shift arrays (14, 16, 18) respectively, and the outputs of the three sense amps (24, 26, 28) are coupled to the input of a logic-OR gate (30) which has as its output an Indicator Bit signal. The word, nibble and bit shift arrays (14, 16, 18) are coupled to control decode circuit (22) which receives and decodes information from a Microcode Control Bus and from three shift count control buses. Parallel data bits are input to the bidirectional variable bit shifter (10) through the latch/input driver (12), and shifted 0, 16, 32, 48, 64 or 80 bits by the word shift array (14), 0, 4, 8, or 12 bits by the nibble shift array (16), and 0, 1, 2 or 3 bits by the bit shift array (18). The word, nibble and bit shift arrays (14, 16 and 18) send signals to the sense amps (24, 26, 28) respectively when significant data bits are shifted right of the least significant bit on right shift operations which in turn signal logic-OR gate (30). The control decode circuit (22) controls the direction of shfits, the number of bit positions shifted, and the fill node within the word, nibble and bit shift arrays (14, 16, 18).

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Carrollton, TX, United States of America

Robert D Maher, Iii