Hewlett-Packard Development Company, L.p.

Robert D Bushey

Kelly Larson

Michelle R Lehmeier

Michelle A Watson

A multiple function image capture and serving apparatus that comprises a processor unit having firmware memory with instructions for implementing an operating system and random access memory for receiving at least one executable code sections for performing a selected one of a plurality of image capture tasks; a network access module for communicatively connecting the processor unit to an ICA code server, wherein the processor unit in response to executing the operating system and selection of the task by a user is adapted to request and receive from the server at least one executable code sections for performing the selected task; and an image capture module for receiving and converting a visual image into a digital image signal and making said signal available to the processor unit for performing upon it the selected task pursuant to execution of the at least one received executable code sections.

Dynamically programmable image capture appliance and system

Generally, graphics are displayed on a monitor or printed on an output device after a series of steps are performed, typically implemented in the form of a graphics pipeline, in the case of an object-oriented graphic image. Similarly, a digital picture or digital video image passes through a digital pipeline for the digital image or images to be displayed, printed, or otherwise processed. The present invention encompasses a system and method in which the stages of the graphics pipeline used to process a graphic object are interconnected to the stages of the digital pipeline used to process a bit-mapped image so that a single, interconnected pipeline can be used to process object-oriented graphic images, bit map images and/or images which contain graphics and bit map portions. This interconnected pipeline can be used to process images through various stages of the graphics pipeline followed by stages typically contained in the digital pipeline, or vice versa, to create desired effects. This interconnected pipeline includes a switch or a selectively configurable interconnection matrix which defines an image path which connects desired stages of the pipeline.

System and method for combining graphics formats in a digital video pipeline

A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

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San Diego, CA, United States of America

Robert D Bushey