Xerox Corporation

Motorola Corporation

Robert D Berger

Mark B Weaver

Dwight D Esgar

M Nghiem Phan

An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block. Isolation blocks (14-20) receive control signals from the bias control logic circuit (12) to isolate the idle functional block and to provide a predetermined logic level in the signal paths from the idle functional to prevent propagation of an erroneous signal.

Circuit and method for isolating circuit blocks for reducing power

A high speed voltage translator is responsive to an ECL input signal for providing a TTL output signal at an output while clamping the low output voltage thereof to a predetermined value. The ECL input signal is converted to first and second complementary control signals for driving the upper and lower transistors in the output stage, respectively. The second control signal enables a third transistor, the base of which is connected via a serial diode and resistor combination to a second collector of the lower transistor in the output stage. The base-emitter junction potential of the third transistor cancels the potential across the diode whereby the collector of the lower transistor that is the output of the voltage translator is clamped at one base-emitter junction potential less the voltage across the resistor. Furthermore, the current flowing through the resistor is compensated for temperature variation whereby the low output voltage is independent of temperature. The first and second control signals enable separate charge and discharge paths for the upper and lower transistors whereby the associated propagation delays may be controlled so as to inhibit simultaneous conduction through the output stage.

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Chandler, AZ, United States of America

Robert D Berger