Wang Laboratories, Inc.

Sun Microsystems, Inc.

Other

Robert D. Becker

Anthony S. Fong

Martin J. Schwartz

Janis Delmonte

Robert D Becker

Martin J Schwartz

Peter A Mehring

Kevin H Curcuru

Richard W Coyle

Anthony S Fong

Varoujan Garapetian

Kenneth J Eng

Richard F Giunta

Construction set element

A calculator mount includes a self closing hinge with a frame wing and a door wing. The frame wing is attached to a desk with a top and overhang, and a calculator mounting bracket is carried by the door wing. The door wing and bracket swing between a position at which the calculator is at a position adjacent the top surface of the desk and a position at which it folds under the desk. It can be mounted on either side of the desk.

Calculator mount

A translation lookaside buffer for use with a virtual memory system including apparatus for storing virtual addresses, apparatus for storing a physical address associated with each of the virtual addresses, some of the physical addresses corresponding to pages in which the information sought by the virtual address resides, and others of the physical addresses corresponding to pages in which the physical address of information sought by the virtual address resides.

Translation lookaside buffer apparatus and method with input/output

A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus. The reading logic includes read request receiving and buffer logic having a plurality of storage locations for storing received read requests and associated read addresses prior to the execution of the read requests. The memory control unit further has logic for comparing a received read address to write addresses stored in the write address buffer, the comparing logic having an output for indicating, when asserted, the occurence of the reception of a read address having a value within a predetermined range of values of one of the stored write addresses.

Memory control unit with selective execution of queued read and write

A translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessable and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, including a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, apparatus for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and apparatus for ascertaining whether the virtual address held in the apparatus for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of the plurality of sources and for another of the plurality of sources simultaneously.

Apparatus for increasing the number of hits in a translation lookaside

In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing the memory requests, the MMU is able to maintain an account of each memory access, thereby providing the MMU the means to determine if a memory access fulfills the requirements of a fast page mode access before a request is made to the MCU. The MMU comprises the row address comparator which can execute the row address comparison in parallel with the cache lookup. Therefore, if the cache lookup determines a memory access is required, a specific fast page mode memory access request can be made, without the memory controller incurring the additional delay of checking the row address. Thus, by using the memory access unit of the present invention, the system can default to fast page mode access without the additional penalty normally incurred by comparing the row address in a serial manner.

Method and apparatus for increasing the speed of memory access in a

A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus. The dual functionality of the first group of signal lines eliminates the requirement for separate and dedicated command/ID and data signal line paths and associated driving and receiving circuit elements.

System bus having multiplexed command/ID and data

A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.

Apparatus and method for a space saving translation lookaside buffer for

A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storage position have been modified (dirty) since those contents were received from main memory. Another status indication indicates whether the contents of the storage position exist within another cache memory (shared). Each cache includes a bus monitor that monitors bus transactions. When data is read from system memory by a first cache a second cache determines if the data is shared. If yes, the second cache asserts a bus hold line and determines if the shared data is dirty. If yes, the second cache drives the corresponding data to the bus for storage within the first cache. For a system memory write, the second cache latches the data and determines if the data is shared. If yes, the second cache replaces its copy of the data with that latched from the bus. As such, no cache 'valid' status bits are required in that each cache is assured of having the most current version of data.

Multi-processor system with cache memories

Apparatus for executing a conditional branch instruction in a pipelined processing unit which has an instruction queue for storing an instruction stream, address generating apparatus connected to the head of the instruction queue for generating and retaining an address defined in the portion of the instruction stream presently at the head of the instruction queue, and instruction interpretation apparatus which is also connected to the head of the instruction queue for receiving and interpreting an instruction at the head of the instruction queue. A conditional branch instruction which is presently at the head of the instruction queue is executed by first performing a dispatch operation in a first cycle which is the last cycle of execution of the instruction preceding the conditional branch instruction in the instruction queue. The dispatch operation sets up the execution of the instruction at the head of the instruction queue. One result of the dispatch operation is the generation of the address for the target instruction specified in the branch instruction. Thereupon, in an immediately following second cycle, a conditional fetch operation and a test operation are performed. The conditional fetch operation provides the address for the target instruction to the processing unit's memory. The test operation determines whether the branch is to be taken. If the branch is not to be taken, the target instruction is not loaded into the instruction queue, the cycle is extended, and a dispatch operation is performed in the extended cycle. If the branch is to be taken, the target instruction is loaded into the head of the instruction queue in the second cycle. Finally, when the branch is taken, the dispatch operation is performed in an immediately following third cycle.

Apparatus and method for executing a conditional branch instruction

A system console 30 is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays 16-22. The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array 40, one of which is disposed upon each of the memory boards 12 and 14 and also upon a memory controlling unit 26, the memory logic arrays being coupled together by a bit serial scan bus 42. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all subsequent memory boards.

Memory diagnostic apparatus and method

A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether the contents of a storage position have been modified since those contents were received from main memory and another indicates whether the contents of the storage position may be present elsewhere memory means. Control means are provided to assure that when a data unit from a CPU is received and stored in the CPU's associated cache memory means, which data unit is indicated as being also stored in a cache memory means associated with another CPU, such CPU data unit is also written into main memory means. During that process, other cache memory means monitor the bus means and update its corresponding data unit. Bus monitor means are provided and monitor all writes to main memory and reads from main memory to aid in the assurance of system-wide data integrity.

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Shirley, MA, United States of America

Robert D Becker