Intel Corporation

Marvell International Limited

Robert D Bateman

Kayla L Chalmers

James R Harness

Lawrence T Clark

Winston Lee

Kit Sang Tam

David Lippincott

Kresten V McGrath

In some implementations, a built-in self-test (BIST) circuitry of a memory device is configured to perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated, enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error, detect an error in data read from the memory device after enabling error logging, and store information associated with the detected error.

Test data reporting during memory testing

A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

Byte aligned redundancy for memory array

Briefly, in accordance with one embodiment of the invention, a method by which one or more ways of a cache may be locked so that they are not overwritten with data. Further, the ways of a cache that are locked may be given higher priority than the most recently used or accessed ways.

Cache having a prioritized replacement technique and method therefor

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

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Phoenix, AZ, United States of America

Robert D Bateman